View ADUC7128_1158432.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Precision Analog Microcontroller ARM7TDMI(R) MCU with 12-bit ADC & DDS DAC Preliminary Technical Data
FEATURES
Analog I/O Multi-Channel, 12-bit, 1MSPS ADC - 10 ADC channels - Fully differential and single-ended modes - 0 to VBREFB Analog Input Range 10-bit DAC - 32-bit 21MHz DDS - Current-to-Voltage (I/V) Conversion - Integrated 2Pnd order LPF - DDS Input to DAC - 100ohm Line Driver On-Chip Voltage Reference On-Chip Temperature Sensor (3C) Uncommitted Voltage Comparator Microcontroller ARM7TDMI Core, 16/32-bit RISC architecture JTAG Port supports code download and debug External Watch crystal/ Clock Source - 41.78 MHz PLL with 8 way Programmable Divider - Optional Trimmed On-Chip Oscillator
P
ADUC7128
Memory 126k Bytes Flash/EE Memory, 8k Bytes SRAM In-Circuit Download, JTAG based Debug Software triggered in-circuit re-programmability On-Chip Peripherals 2 x UART, 2 x IP2 and SPI Serial I/O 28-Pin GPIO Port 5 X General Purpose Timers Wake-up and Watchdog Timers Power Supply Monitor 16-bit PWM generator Quadrature Encoder PLA - Programmable Logic (Array) Power Specified for 3V operation Active Mode: 11mA (@5MHz) 45mA (@41.78 MHz) Packages and Temperature Range 64 lead LFCSP (9mm x 9mm) package -40C to 85C Tools Low-Cost QuickStart Development System Full Third-Party Support
PC(R)
FUNCTIONAL BLOCK DIAGRAM
DACGND GND REF DACVDD IOGND IOGND AGND IOVDD DGND IOV DD AVD D LVDD
ADC0
CMP0 CMP1 CMP OUT V REF
RST XCLKI XCLKO XCLK
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
Figure 1. Basic Block Diagram Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.comT Tel: 781.329.4700 Fax: 781.326.8703 (c) 2006 Analog Devices, Inc. All rights reserved.
HT H
...
...
...
...
JTAG
P3.0
P3.3
...
...
MUX
T/H TEMP SENSOR
12-BIT SAR ADC 1MSPS
DDS 10-BIT IOUT DAC I/V
VDAC LD1TX LD2TX
+
-
BAND GAP REFERENCE
ADUC7128
PWM1 PWM2 PWM3 PWM 64 KBYTES FLASH/EE (32k x 16 bits) 8192 BYTES SRAM (2k x 32 bits) Quad Encoder PWM4 PWM5 PWM6 S1 S2 2 KBYTES 62 KBYTES FLASH/EE (31k x 16 bits)
ARM7TDMI - BASED MCU WITH ADDITIONAL PERIPHERALS
POR
5 GEN PURPOSE TIMERS WAKE-UP/ RTC TIMER OSC/PLL INTERRUPT CONTROLLER JTAG PLA
PSM
SPI
I2 C
GPIO UART0 UART1 CONTROL
ADUC7128
GENERAL DESCRIPTION
The ADUC7128 is a fully integrated, 1MSPS, 12-bit data acquisition system incorporating a high performance multichannel ADC, DDS with line driver, a 16/32-bit MCU and Flash/EE Memory on a single chip. The ADC consists of up to 10 single-ended inputs. The ADC can operate in single-ended or differential input modes. The ADC input voltage is 0 to VREF. Low drift bandgap reference, temperature sensor and voltage comparator complete the ADC peripheral set. The ADUC7128 also integrates a differential line driver output. This line driver transmits a sine wave whose values are calculated by an on chip DDS or a voltage output determined by the DACDAT MMR.
Preliminary Technical Data
The device operates from an on-chip oscillator and PLL generating an internal high-frequency clock of 41.78 MHz. This clock is routed through a programmable clock divider from which the MCU core clock operating frequency is generated. The microcontroller core is an ARM7TDMI, 16/32-bit RISC machine, offering up to 41 MIPS peak performance. 126k Bytes of non-volatile Flash/EE are provided on-chip as well as 8k Bytes of SRAM. The ARM7TDMI core views all memory and registers as a single linear array. On-chip factory firmware supports in-circuit serial download via the UART and JTAG serial interface ports while nonintrusive emulation is also supported via the JTAG interface. These features are incorporated into a low-cost QuickStart Development System supporting this MicroConverter family. The parts operate from 3.0V to 3.6V and are specified over an industrial temperature range of -40C to 85C. When operating at 41.78 MHz the power dissipation is 150mW. The line driver output if enabled consumes and additional 30mW.
Rev. PrA | Page 2 of 92
Preliminary Technical Data
ADUC7128--SPECIFICATIONS
P B B B B
ADUC7128
Table 1. (AVBDD = IOVBDD = 3.0 V to 3.6 V, VBREF = 2.5 V Internal Reference, fBCORE = 41.78MHz, All specifications TBA = TBMAX to TBMIN, unless otherwise noted.)
B B B
Parameter ADC CHANNEL SPECIFICATIONSP ADC Powerup Time DC Accuracy1,2 Resolution Integral Nonlinearity
P
ADUC7128 5 12 1.5 0.6 2.0 +1/-0.9 0.5 +0.7/-0.6 1 5 1 5 1 69 -78 -75 -80
Unit us
Test Conditions/Comments
Eight acquisition clocks and Fadc/2 Bits LSB max LSB typ LSB typ LSB max LSB typ LSB typ LSB typ LSB max LSB typ LSB max LSB typ Fin = 10kHz Sine Wave, fBSAMPLEB = 1MSPS dB typ dB typ dB typ dB typ 2.5V internal reference 2.5V internal reference 1.0V external reference 2.5V internal reference 2.5V internal reference 1.0V external reference ADC input is a dc voltage
Integral Nonlinearity3 Differential Nonlinearity Differential Nonlinearity3 DC Code Distribution ENDPOINT ERRORS4 Offset Error Offset Error Match Gain Error Gain Error Match DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR)P Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise Channel-to-Channel Crosstalk ANALOG INPUT Input Voltage Ranges Differential mode5 Single-ended mode Leakage Current
TP PT P
Input Capacitance ON-CHIP VOLTAGE REFERENCE Output Voltage Accuracy Reference Temperature Coefficient Power Supply Rejection Ratio Output Impedance Internal VBREFB Power-On Time EXTERNAL REFERENCE INPUT6 Input Voltage Range Input Impedance DAC CHANNEL SPECIFICATIONS VDAC Output Voltage Swing I/V output resistance Low Pass Filter 3db point
VBCMBVBREFB/2 0 to VBREFB 6 1 20 2.5 5 40 75 70 1 0.625 AVBDDB 65
Volts Volts A max A typ pF typ V mV max ppm/C typ dB typ typ ms typ V min V max K typ
During ADC Acquisition 0.47F from VBREFB to AGND Measured at TBA = 25C
B
0.33*VBREFB 0.2*VBREFB 500 1 1.5 2 10
Resolution
max MHz min MHz typ MHz max Bits
RBL = 5k, CBL = 100pF VBREFB is the internal 2.5V reference V mode selected
B B
2-pole.
Rev. PrA | Page 3 of 92
ADUC7128
Parameter Relative Accuracy Differential Nonlinearity, +'ve Differential Nonlinearity, -'ve Offset Error Gain Error Voltage Output Settling Time to 0.1% Line Driver Output Total Harmonic Distortion Output Voltage Swing ADUC7128 2 0.25 1.5 TBD TBD TBD 600 Unit LSB typ LSB Typ LSB Typ mV max mV max mV typ ns max
Preliminary Technical Data
Test Conditions/Comments
DDS Mode DAC Mode As measured into a range of specified loads (see Figure 2) at PL1/LD2TX unless otherwise noted DDS operating at 691.2kHz.
Common Mode
0.30 TBD 1.753 1.768 1.782 TBD
% typ % max V min RMS V typ RMS V max RMS V typ
TBD
V typ
Differential Input Impedance Leakage current LD1TX, LD2TX Leakage current LDIN Short Circuit Current Digital to Analog Glitch Energy Line Driver Tx Powerup time COMPARATOR Input Offset Voltage Input Bias Current Input Voltage Range Input Capacitance Hysteresis3,5 Response Time TEMPERATURE SENSOR Voltage Output at 25C Voltage TC Accuracy POWER SUPPLY MONITOR (PSM) IOVDD Trip Point Selection Power Supply Trip Point Accuracy Glitch Immunity on RESET Pin3 Watchdog Timer (WDT) Timeout Period
10 12.5 5 5 50 TBD 20 15 1 AGND to AVBDDB-1.2 7 2 15 1
k min k typ uA max uA max mA nVsec typ s max mV typ A typ Vmin/Vmax pF typ mV min mv max s typ
AC Mode Each output has a common mode of 0.5*AVBDDB and swings 0.5*VBREFB above and below this. VBREFB is the internal 2.5V reference DC Mode Each output has a common mode of 0.5*VBREFB and swings 0.5*VBREFB above and below this. VBREFB is the internal 2.5V reference Line Driver Buffer disabled Line Driver Buffer disabled
I LSB change at major carry
Hysteresis can be turned on or off via the CMPHYST bit in the CMPCON register Response time may be modified via the CMPRES bits in the CMPCON register
780 -1.3 3
mV typ mV/C typ C typ
2.79 3.07 2.5 50 0 512
V V % typ s typ ms min s max
Rev. PrA | Page 4 of 92
Two selectable Trip Points Of the selected nominal Trip Point Voltage
Preliminary Technical Data
Parameter Flash/EE MEMORY7,8 Endurance Data Retention Digital Inputs Logic 1 Input Current (leakage Current ) Logic 0 Input Current (leakage Current ) ADUC7128 10,000 20 Unit Cycles min Years min Test Conditions/Comments
ADUC7128
TBJ = 85C
B
1 0.2 -60 -40 -120 -80 10 0.8 2.0
A max A typ A max A typ A max
All digital inputs including XCLKI and XCLKO VINH = VDD or VINH = 5V VINL = 0V, except TDI VINL = 0V, TDI Only
A typ
pF typ All Logic inputs including XCLKI and XCLKO V max V min
Input Capacitance Logic Inputs3 VINL, Input Low Voltage VINH, Input High Voltage Quadrature Encoder Inputs S1/S2/CLR (Schmitt-Triggered Inputs) VBT+ VBTVBT+B -VBT-B Logic Outputs9 VOH, Output High Voltage VOL, Output Low Voltage CRYSTAL INPUTS XCLKI and XCLKO Logic Inputs, XCLKI Only VINL, Input Low Voltage VINH, Input High Voltage XCLKI Input Capacitance XCLKO Output Capacitance MCU CLOCK RATE (PLL)
1.9 2.1 0.9 1.1 0.9 1.1 IOVBDDB - 400mV 0.4
V min V max V min V max V min V max V min V max IBSOURCEB = 1.6mA IBSINKB = 1.6mA
1.1 1.7 20 20
V V pF pF 8 programmable core clock selections within this range. (32.768kHz x 1275)/128 (32.768kHz x 1275)/1
INTERNAL OSCILLATOR Tolerance STARTUP TIME At Power-On From Pause/Nap Mode From Sleep Mode From Stop Mode Programmable Logic Array (PLA) Pin Propagation Delay
326.4 41.779200 32.768 3 TBD TBD TBD TBD 12
kHz min MHz max kHz typ % max
Core Clock = 41.78 MHz
ns typ
From input pin to output pin
Rev. PrA | Page 5 of 92
ADUC7128
Parameter Element Propagation Delay ADUC7128 2.5 Unit ns typ
Preliminary Technical Data
Test Conditions/Comments
POWER REQUIREMENTS Power Supply Voltage Range IOVBDDB, AVBDDB and DACVBDD (Supply Voltage to Chip) LVBDDB (Regulator Output from Chip) Power Supply Current10,11 Normal Mode
3.0 3.6 2.5 2.6 2.7 15 17 42 45 30 30 250 400
V min V max V min V typ V max mA typ mA max mA typ mA max mA max mA max A typ A max 5.52MHz clock 5.52MHz clock 41.78MHz clock 41.78MHz clock 691kHz, max load (Fig. 2) 44.2MHz clock External Crystal or Internal Osc ON
Additional Line Driver Tx Supply Current Pause Mode Sleep Mode
1 2
All ADC channel specifications are guaranteed during normal MicroConverter core operation. Apply to all ADC input channels. 3 Not production tested but supported by design and/or characterization data on production release. 4 Measured using an external AD845 op amp as an input buffer stage as shown in Figure 38. Based on external ADC system components. 5 The input signal can be centered on any dc common-mode voltage (VCM) as long as this value is within the ADC voltage input range specified. 6 When using an external reference input pin, the internal reference must be disabled by setting the LSB in the REFCON memory mapped register to 0. 7 Endurance is qualified as per JEDEC Std. 22 method A117 and measured at -40C, +25C, and +85C. 8 Retention lifetime equivalent at junction temperature (Tj) = 85C as per JEDEC Std. 22 method A117. Retention lifetime derates with junction temperature. 9 Test carried out with a maximum of 8 I/O set to a low output level. 10 Power supply current consumption is measured in normal, pause and sleep modes under the following conditions: Normal Mode: 3.6 V supply, Pause Mode: 3.6 V supply, Sleep Mode: 3.6 V supply 11 IOVDD power supply current decreases typically by 2 mA during a Flash/EE erase cycle.
Rev. PrA | Page 6 of 92
Preliminary Technical Data
100nF LD1TX 94 118 100nF LD2TX 27.5uH
ADUC7128
94
100nF LD1TX 94 57 100nF LD2TX
Figure 2. Line Driver Load min (top) and max (bottom)
8.9uH
94
Rev. PrA | Page 7 of 92
ADUC7128
Table 2. IP2 Timing in Fast Mode (400 kHz)
PC
Preliminary Technical Data
Parameter tBLOWB tBHIGHB tBHD;STAB tBSU;DATB tBHD;DATB tBSU;STAB tBSU;STOB tBBUFB tBR tBF tBSUPB
B B
Description SCLOCK low pulsewidthT1 SCLOCK high pulsewidth1 Start condition hold time Data setup time Data hold time Setup time for repeated start STOP condition setup time Bus-free time between a STOP condition and a START condition Rise time for both CLOCK and SDATA Fall time for both CLOCK and SDATA Pulsewidth of spike suppressed
P PT P.
Min 200 100 300 100 50 100 100 1.3 100 60
Slave Max
Master Typ 1360 1140 251350 740 400 12.51350 400 200 20
Unit ns ns ns ns ns ns
300 100 50
ns ns ns
1
TP PT
tBHCLKB depends on the clock divider or CD bits in PLLCON MMR. THCLK = tBUCLKB/2PCD
tBUF
SDATA (I/O)
tSUP tR
MSB LSB ACK MSB
tDSU tPSU tSHD
SCLK (I) PS STOP START CONDITION CONDITION 1 2-7
tDHD tH
8
tDSU tRSU
9
tF tDHD tR
1 S(R) REPEATED START
Figure 3. IP2 Compatible Interface Timing
PC
Rev. PrA | Page 8 of 92
04955-054
tL
tSUP
tF
Preliminary Technical Data
Table 3. SPI Master Mode Timing (PHASE Mode = 1)
Parameter tBSLB tBSHB tBDAVB tBDSUB tBDHDB tBDFB tBDRB tBSRB tBSFB
1
TP PT
ADUC7128
Description SCLOCK low pulsewidthT1
P PT
Min
SCLOCK high pulsewidth1 Data output valid after SCLOCK edge Data input setup time before SCLOCK edgeT2 Data input hold time after SCLOCK edge2 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time
P PT P.
Typ (SPIDIV + 1) x tBHCLKB (SPIDIV + 1) x tBHCLKB
Max
Unit ns ns
2 x tBHCLK + 2 x tBUCLKB 1 x tBUCLKB 2 x tBUCLKB 5 5 5 5 12.5 12.5 12.5 12.5
ns ns ns ns ns ns ns
2
TP PT
tBHCLKB depends on the clock divider or CD bits in PLLCON MMR. TBHCLKB = tBUCLKB/2PCD tBUCLKB = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
SCLOCK (POLARITY = 0) SCLOCK (POLARITY = 1)
tSH tSL tSR tSF
tDAV
MOSI MSB
tDF
tDR
BITS 6-1 LSB
MISO
MSB IN
BITS 6-1
LSB IN
04955-055
tDSU tDHD
Figure 4. SPI Master Mode Timing (PHASE Mode = 1)
Rev. PrA | Page 9 of 92
ADUC7128
Preliminary Technical Data
Table 4. SPI Master Mode Timing (PHASE Mode = 0)
Parameter tBSLB tBSHB tBDAVB Description SCLOCK low pulsewidthT1 SCLOCK high pulsewidth1 Data output valid after SCLOCK edge
P PT
Min
Typ (SPIDIV + 1) x tBHCLKB (SPIDIV + 1) x tBHCLKB
Max
tBDOSUB tBDSUB tBDHDB tBDFB tBDRB tBSRB tBSFB
1
TP PT
Data output setup before SCLOCK edge Data input setup time before SCLOCK edgeT2 Data input hold time after SCLOCK edge2 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time
P PT P.
2x tBHCLK + 2x tBUCLKB 75 1 x tBUCLKB 2 x tBUCLKB 5 5 5 5 12.5 12.5 12.5 12.5
Unit ns ns ns
ns ns ns ns ns ns ns
2
TP PT
tBHCLKB depends on the clock divider or CD bits in PLLCON MMR. TBHCLKB = tBUCLKB/2PCD tBUCLKB = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
SCLOCK (POLARITY = 0)
tSH tSL tSR
SCLOCK (POLARITY = 1)
tSF
tDOSU
MOSI MSB
tDAV tDF tDR
BITS 6-1 LSB
MISO
MSB IN
BITS 6-1
LSB IN
tDHD
Figure 5. SPI Master Mode Timing (PHASE Mode = 0)
Rev. PrA | Page 10 of 92
04955-056
tDSU
Preliminary Technical Data
ADUC7128
Table 5. SPI Slave Mode Timing (PHASE Mode = 1)
Parameter tBCSB tBSLB tBSHB tBDAVB Description CS to SCLOCK edgeT1 SCLOCK low pulsewidthT2 SCLOCK high pulsewidth2 Data output valid after SCLOCK edge
P PT P PT
Min 2 x tBUCLKB
Typ (SPIDIV + 1) x tBHCLKB (SPIDIV + 1) x tBHCLKB
Max
2x tBHCLK + 2x tBUCLKB 1 x tBUCLKB 2 x tBUCLKB 5 5 5 5 0 12.5 12.5 12.5 12.5
Unit ns ns ns ns
tBDSUB tBDHDB tBDFB tBDRB tBSRB tBSFB tBSFSB
1
TP PT
Data input setup time before SCLOCK edge1 Data input hold time after SCLOCK edge1 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time CS high after SCLOCK edge
ns ns ns ns ns ns ns
2
TP PT
tBUCLKB = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. tBHCLKB depends on the clock divider or CD bits in PLLCON MMR. TBHCLKB = tBUCLKB/2PCD
P.
CS
tCS
SCLOCK (POLARITY = 0)
tSFS
tSH tSL tSR
SCLOCK (POLARITY = 1)
tSF
tDAV
MISO MSB
tDF
tDR
BITS 6-1 LSB
MOSI
MSB IN
BITS 6-1
LSB IN
04955-057
tDSU tDHD
Figure 6. SPI Slave Mode Timing (PHASE Mode = 1)
Rev. PrA | Page 11 of 92
ADUC7128
Preliminary Technical Data
Table 6. SPI Slave Mode Timing (PHASE Mode = 0)
Parameter tBCSB tBSLB tBSHB tBDAVB Description CS to SCLOCK edgeT1 SCLOCK low pulsewidthT2 SCLOCK high pulsewidth2 Data output valid after SCLOCK edge
P PT P PT
Min 2 x tBUCLKB
Typ (SPIDIV + 1) x tBHCLKB (SPIDIV + 1) x tBHCLKB
Max
2x tBHCLK + 2x tBUCLKB 1 x tBUCLKB 2 x tBUCLKB 5 5 5 5 0 12.5 12.5 12.5 12.5 25
Unit ns ns ns ns
tBDSUB tBDHDB tBDFB tBDRB tBSRB tBSFB tBDOCSB tBSFSB
1
TP PT
Data input setup time before SCLOCK edge1 Data input hold time after SCLOCK edge1 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time Data output valid after CS edge CS high after SCLOCK edge
ns ns ns ns ns ns ns ns
2
TP PT
tBUCLKB = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. tBHCLKB depends on the clock divider or CD bits in PLLCON MMR. TBHCLKB = tBUCLKB/2PCD
P.
Rev. PrA | Page 12 of 92
Preliminary Technical Data
ADUC7128
CS
tCS
SCLOCK (POLARITY = 0)
tSFS
tSH
SCLOCK (POLARITY = 1)
tSL tSR tSF
tDAV tDOCS tDF
MISO MSB
tDR
BITS 6-1 LSB
MOSI
MSB IN
BITS 6-1
LSB IN
04955-058
tDSU tDHD
Figure 7. SPI Slave Mode Timing (PHASE Mode = 0)
Rev. PrA | Page 13 of 92
ADUC7128
ABSOLUTE MAXIMUM RATINGS
TBA = 25C unless otherwise noted. DVBDDB = IOVBDDB, AGND = REFGND = DACGND = GNDBREF.B
B
Preliminary Technical Data
Table 7.
Parameter AVBDDB to DVBDDB AGND to DGND IOVBDDB to IOGND, AVBDDB to AGND Digital Input Voltage to IOGND Digital Output Voltage to IOGND VBREFB to AGND Analog Inputs to AGND Analog Output to AGND Operating Temperature Range Industrial ADUC7128 Storage Temperature Range Junction Temperature BJAB Thermal Impedance (64-pin CSP) Peak Solder Reflow Temperature SnPb Assemblies (10 sec to 30 sec) PbFree Assemblies (20 sec to 40 sec) Rating -0.3 V to +0.3 V -0.3 V to +0.3 V -0.3 V to +6 V -0.3 V to IOVBDDB + 0.3 V -0.3 V to IOVBDDB + 0.3 V -0.3 V to AVBDDB + 0.3 V -0.3 V to AVBDDB + 0.3 V -0.3 V to AVBDDB + 0.3 V -40C to +85C -65C to +150C 125C 24C/W 240C 260C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrA | Page 14 of 92
Preliminary Technical Data
PIN FUNCTION DESCRIPTIONS - ADUC7128
Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Mnemonic ADC5 VDACout ADC9 ADC10 GNDBREFB ADCNEG AVBDDB ADC12/LD1TX ADC13/ LD2TX AGND TMS TDI P4.6/SPM10 P4.7/SPM11 P0.0/BM/CMPBOUTB P0.6/T1/MRST TCK TDO IOGND IOVBDDB LVBDDB DGND P3.0/PWM1 P3.1/PWM2 P3.2/PWM3 P3.3/PWM4 P0.3/ADCBBUSYB/TRST RST P3.4/PWM5 P3.5/PWM6 P0.4/IRQ0/CONVST P0.5/IRQ1/ADCBBUSYB P2.0/SPM9 P0.7/SPM8/ECLK/XCLK XCLKO XCLKI PVBDDB Type I I I I S I S I/O I/O S I I I.O I.O I/O O I O S S S S I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O O I S Function
ADUC7128
Single-ended or differential Analog input 5 / Line Driver input Output from DAC buffer Single-ended or differential Analog input 9 Single-ended or differential Analog input 10 Ground voltage reference for the ADC. For optimal performance the analog power supply should be separated from IOGND and DGND Bias point or Negative Analog Input of the ADC in pseudo differential mode. Must be connected to the ground of the signal to convert. This bias point must be between 0V and 1V Analog Power Single-ended or differential Analog input 12 / DAC differential negative output Single-ended or differential Analog input 13 / DAC differential Positive output Analog Ground. Ground reference point for the analog circuitry JTAG Test Port Input - Test Mode Select. Debug and download access JTAG Test Port Input - Test Data In. Debug and download access General Purpose Input-Output Port 4.6 / Serial Port Mux pin 10 General Purpose Input-Output Port 4.7 / Serial Port Mux pin 11 General Purpose Input-Output Port 0.0 /Boot Mode. The ADUC7128 will enter download mode if BM is low at reset and will execute code if BM is pulled high at reset through a 1kOhm resistor/ Voltage Comparator Output General Purpose Output Port 0.6 / Timer 1 Input / Power on reset output JTAG Test Port Input - Test Clock. Debug and download access JTAG Test Port Output - Test Data Out. Debug and download access Ground for GPIO. Typically connected to DGND 3.3V Supply for GPIO and input of the on-chip voltage regulator. 2.5V. Output of the on-chip voltage regulator. Must be connected to a 0.47F capacitor to DGND Ground for core logic. General Purpose Input-Output Port 3.0/ PWM 1 output General Purpose Input-Output Port 3.1/ PWM 2 output General Purpose Input-Output Port 3.2/ PWM 3 output General Purpose Input-Output Port 3.3/ PWM 4 output General Purpose Input-Output Port 3.3/ ADCBBUSYB signal / JTAG Test Port Input - Test Reset. Debug and download access Reset Input. (active low) General Purpose Input-Output Port 3.4/ PWM 5 output General Purpose Input-Output Port 3.5/ PWM 6 output General Purpose Input-Output Port 0.5 / External Interrupt Request 0, active high / Start conversion input signal for ADC General Purpose Input-Output Port 0.6 / External Interrupt Request 1, active high / ADCBBUSYB signal General Purpose Input-Output Port 2.0 / Serial Port Mux pin 9 General Purpose Input-Output Port 0.7 / Serial Port Mux pin 8 / Output for External Clock signal/ Input to the internal clock generator circuits Output from the crystal oscillator inverter Input to the crystal oscillator inverter and input to the internal clock generator circuits 2.5V.PLL supply. Must be connected to a 0.1F capacitor to DGND Should be connected to 2.5V LDO output.
Rev. PrA | Page 15 of 92
ADUC7128
Pin# 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Mnemonic DGND P1.7/SPM7 P1.6/SPM6 IOGND IOVBDDB P4.0/S1 P4.1/S2 P1.5/SPM5 P1.4/SPM4 P1.3/SPM3 P1.2/SPM2 P1.1/SPM1 P1.0/SPM0 P4.2 P4.3/ PWMBTRIPB P4.4 P4.5 VBREFB DACGND AGND AVBDDB DACVBDDB ADC0 ADC1 ADC2/CMP0 ADC3/CMP1 ADC4 Type S I/O I/O S S I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O S S S S I I I I I Function
Preliminary Technical Data
Ground for PLL. General Purpose Input-Output Port 1.7/Serial Port Mux pin 7 General Purpose Input-Output Port 1.6/Serial Port Mux pin 6 Ground for GPIO. Typically connected to DGND 3.3V Supply for GPIO and input of the on-chip voltage regulator. General Purpose Input-Output Port 4.0/ Quadrature Input 1 General Purpose Input-Output Port 4.1 / Quadrature Input 2 General Purpose Input-Output Port 1.5/Serial Port Mux pin 5 General Purpose Input-Output Port 1.4/Serial Port Mux pin 4 General Purpose Input-Output Port 1.3/Serial Port Mux pin 3 General Purpose Input-Output Port 1.2/Serial Port Mux pin 2 General Purpose Input-Output Port 1.1/Serial Port Mux pin 1 General Purpose Input-Output Port 1.0/Serial Port Mux pin 0 General Purpose Input-Output Port 4.2 General Purpose Input-Output Port 4.3/ PWM safety cut off General Purpose Input-Output Port 4.4 General Purpose Input-Output Port 4.5 2.5V internal Voltage Reference. Must be connected to a 0.47uF capacitor when using the internal reference. Ground for the DAC. Typically connected to AGND Analog Ground. Ground reference point for the analog circuitry Analog Power Power Supply for the DAC, This must be supplied with 2.5V. This can be connected to the LDO output. Single-ended or differential Analog input 0 Single-ended or differential Analog input 1 Single-ended or differential Analog input 2/ Comparator positive input Single-ended or differential Analog input 3/ Comparator negative input Single-ended or differential Analog input 4
Rev. PrA | Page 16 of 92
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS
1.0 0.8 0.6 0.4 0.2
(LSB)
ADUC7128
1.0
fS = 774kSPS
fS = 774kSPS
0.8 0.6 0.4 0.2
(LSB)
04955-075
0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1000 2000 ADC CODES
B
0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1000 2000 ADC CODES 3000 4000
04955-074
3000
4000
Figure 8. Typical INL Error, fBS = 774 kSPS
1.0 1.0
Figure 11. Typical DNL Error, fs = 774 kSPS
fS = 1MSPS
0.8 0.6 0.4 0.2
(LSB)
fS = 1MSPS
0.8 0.6 0.4 0.2
(LSB)
0 -0.2 -0.4 -0.6
04955-077
0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1000 2000 ADC CODES
B
-0.8 -1.0 0 1000 2000 ADC CODES
B
3000
4000
3000
4000
Figure 9. Typical INL Error, fBS = 1 MSPS
1.0 0.9 0.8 0.7 WCP 0.6
(LSB) (LSB)
Figure 12. Typical DNL Error, fBS = 1 MSPS
0 -0.1 -0.2 -0.3
(LSB)
0 -0.1 -0.2 WCN -0.3 -0.4
1.0 0.9 0.8 0.7 0.6 0.5 WCP 0.4 0.3 0.2 0.1 1.0 1.5 2.0 2.5 EXTERNAL REFERENCE (V)
B
0.5 -0.6 0.4 WCN 0.3 0.2 0.1 0 1.0 1.5 2.0 2.5 EXTERNAL REFERENCE (V)
B
-0.5 -0.6
-0.7 -0.8
04955-072
-0.7 -0.8 -0.9 -1.0 3.0
-0.9 -1.0
3.0
0
Figure 10. Typical Worse Case INL Error vs. VBREFB, fBS = 774 kSPS
Figure 13. Typical Worse Case DNL Error vs. VBREFB, fBS = 774 kSPS
Rev. PrA | Page 17 of 92
04955-071
(LSB)
-0.5
04955-076
ADUC7128
9000 8000 7000
Preliminary Technical Data
75 -76 70 SNR 65 -78
6000
FREQUENCY
-80
SNR (dB)
5000 4000 3000
60 THD 55 -84 50 -82
2000 1000 0
04955-070
04955-073
45
-86
1161
1162 BIN
1163
40
1.0
1.5
2.0 2.5 EXTERNAL REFERENCE (V)
3.0
-88
Figure 14. Code Histogram Plot
0 -20 -40
1350 1500
Figure 17. Typical Dynamic Performance vs. VBREFB
fS = 774kSPS, SNR = 69.3dB, THD = -80.8dB, PHSN = -83.4dB
1450 1400
-60
CODE
(dB)
1300 1250 1200 1150
-80 -100 -120
1100
04955-078
1050 1000 -50 0 50 TEMPERATURE (C) 100 150
-160
0
100 FREQUENCY (kHz)
B
200
Figure 15. Dynamic Performance, fBS = 774 kSPS
20 0 -20 -40
Figure 18. On-Chip Temperature Sensor Voltage Output vs. Temperature
39.8 39.7 39.6 39.5
fS = 1MSPS, SNR = 70.4dB, THD = -77.2dB, PHSN = -78.9dB
(dB)
-60 -80 -100
39.2
(mA)
39.4 39.3
-120 -140 -160
04955-079
39.1 39.0 38.9
04955-080
0
50
100 FREQUENCY (kHz)
B
150
200
-40
0
Figure 16. Dynamic Performance, fBS = 1 MSPS
25 85 TEMPERATURE (C)
125
Figure 19. Current Consumption vs. Temperature @ CD = 0
Rev. PrA | Page 18 of 92
04955-060
-140
THD (dB)
Preliminary Technical Data
12.05 12.00 11.95 11.90 11.85
ADUC7128
Current consumption in sleep mode
300 250 200
(mA)
11.80
uA
04955-081
11.75 11.70 11.65 11.60 11.55 -40 0 25 85 TEMPERATURE (C) 125
150 100 50 0 -40 25 85 125 TEMPERATURE (DEGREE C)
Figure 20. Current Consumption vs. Temperature @ CD = 3
7.85 7.80 7.75 7.70 37.0 37.2
Figure 22. Current Consumption vs. Temperature in Sleep Mode
37.4
(mA)
7.65 7.60 7.55 36.6 7.50 7.45 7.40
04955-082
(mA)
36.8
36.4
04955-084
-40
0
25 85 TEMPERATURE (C)
125
36.2
62.25
Figure 21. Current Consumption vs. Temperature@t CD = 7
125.00 250.00 500.00 SAMPLING FREQUENCY (kSPS)
1000.00
Figure 23. Current Consumption vs. ADC Speed
Rev. PrA | Page 19 of 92
ADUC7128
TERMINOLOGY
ADC SPECIFICATIONS
Integral Nonlinearity The maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point 1/2 LSB below the first code transition and full scale, a point 1/2 LSB above the last code transition. Differential Nonlinearity The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Offset Error The deviation of the first code transition (0000 . . . 000) to (0000 . . . 001) from the ideal, that is, +1/2 LSB. Gain Error The deviation of the last code transition from the ideal AIN voltage (full scale - 1.5 LSB) after the offset error has been adjusted out. Signal to (Noise + Distortion) Ratio The measured ratio of signal to (noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS2), excluding dc. The ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise.
Preliminary Technical Data
The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by: Signal to (Noise + Distortion) = (6.02 N + 1.76) dB Thus, for a 12-bit converter, this is 74 dB. Total Harmonic Distortion The ratio of the rms sum of the harmonics to the fundamental.
DAC SPECIFICATIONS
Relative Accuracy Otherwise known as endpoint linearity, relative accuracy is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero error and full-scale error. Voltage Output Settling Time The amount of time it takes for the output to settle to within a 1 LSB level for a full-scale input change.
Rev. PrA | Page 20 of 92
Preliminary Technical Data
OVERVIEW OF THE ARM7TDMI CORE
The ARM7 core is a 32-bit Reduced Instruction Set Computer (RISC). It uses a single 32-bit bus for instruction and data. The length of the data can be 8, 16 or 32 bits. The length of the instruction word is 32 bits. The ARM7TDMI is an ARM7 core with 4 additional features: - T support for the Thumb (16 bit) instruction set. - D support for debug - M support for long multiplies - I include the embeddedICE module to support embedded system debugging.
ADUC7128
state, the processor registers can be inspected as well as the Flash/EE, the SRAM and the memory mapped registers.
EXCEPTIONS
ARM supports five types of exceptions, and a privileged processing mode for each type. The five types of exceptions are: 1. Normal interrupt or IRQ. This is provided to service general-purpose interrupt handling of internal and external events. Fast interrupt or FIQ. This is provided to service data transfer or communication channel with low latency. FIQ has priority over IRQ. Memory abort. Attempted execution of an undefined instruction. Software interrupt instruction (SWI). This can be used to make a call to an operating system.
2.
Thumb mode (T)
An ARM instruction is 32-bits long. The ARM7TDMI processor supports a second instruction set that has been compressed into 16-bits, called the thumb instruction set. Faster execution from 16-bit memory and greater code density can usually be achieved by using the thumb instruction set instead of the ARM instruction set, which makes the ARM7TDMI core particularly suitable for embedded applications. However, the thumb mode has two limitations: 1. Thumb code usually uses more instructions for the same job. As a result, ARM code is usually best for maximising the performance of the time-critical code. The thumb instruction set does not include some of the instructions needed for exception handling, which automatically switches the core to ARM code for exception handling.
3. 4. 5.
Typically, the programmer defines interrupt as IRQ, but for higher priority interrupt, that is, faster response time, the programmer can define interrupt as FIQ.
ARM REGISTERS
ARM7TDMI has a total of 37 registers: 31 general purpose registers and six status registers. Each operating mode has dedicated banked registers. When writing user-level programs, 15 general-purpose 32-bit registers (R0 to R14), the program counter (R15) and the current program status register (CPSR) are usable. The remaining registers are only used for system-level programming and for exception handling. When an exception occurs, some of the standard registers are replaced with registers specific to the exception mode. All exception modes have replacement banked registers for the stack pointer (R13) and the link register (R14) as represented in Figure 24. The fast interrupt mode has more registers (R8 to R12) for fast interrupt processing. This means the interrupt processing can begin without the need to save or restore these registers, and thus save critical time in the interrupt handling process.
2.
See the ARM7TDMI user guide for details on the core architecture, the programming model, and both the ARM and ARM thumb instruction sets.
Long Multiply (M)
The ARM7TDMI instruction set includes four extra instructions that perform 32-bit by 32-bit multiplication with 64-bit result, and 32-bit by 32-bit multiplication-accumulation (MAC) with 64-bit result. This result is achieved in fewer cycles than required on a standard ARM7 core.
EmbeddedICE (I)
EmbeddedICE provides integrated on-chip support for the core. The EmbeddedICE module contains the breakpoint and watchpoint registers that allow code to be halted for de-bugging purposes. These registers are controlled through the JTAG test port. When a breakpoint or watchpoint is encountered, the processor halts and enters debug state. Once in a debug
Rev. PrA | Page 21 of 92
ADUC7128
r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 (PC) usable in user mode
Preliminary Technical Data
Memory organisation
The part incorporates three separate blocks of memory, 8kByte of SRAM and two 64kByte of On-Chip Flash/EE memory. 126kByte of On-Chip Flash/EE memory are available to the user, and the remaining 2kBytes are reserved for the factory configured boot page. These two blocks are mapped as shown in Figure 25. Note that by default, after a reset, the Flash/EE memory is mirrored at address 0x00000000. It is possible to remap the SRAM at address 0x00000000 by clearing bit 0 of the REMAP MMR. This remap function is described in more details in the Flash/EE memory chapter.
FFFFFFFFh FFFF0000h
system modes only r8_fiq r9_fiq r10_fiq r11_fiq r12_fiq r13_abt r13_fiq r13_svc r14_abt r14_svc r14_fiq
r13_und r13_irq r14_und r14_irq
CPSR user mode
SPSR_fiq
SPSR_svc
SPSR_abt
SPSR_irq
SPSR_und
MMRs Reserved
fiq mode
svc mode
abort mode
irq undefined mode mode
0009F800h
Flash/EE
Figure 24: register organisation
00080000h
More information relative to the programmer's model and the ARM7TDMI core architecture can be found in the following documents from ARM: - DDI0029G, ARM7TDMI Technical Reference Manual. - DDI0100E, ARM Architecture Reference Manual.
Reserved
00041FFFh 00040000h 0001FFFFh
SRAM Reserved Re-mappable Memory Space (Flash/EE or SRAM)
Interrupt latency
The worst case latency for an FIQ consists of the longest time the request can take to pass through the synchronizer, plus the time for the longest instruction to complete (the longest instruction is an LDM) which loads all the registers including the PC, plus the time for the data abort entry, plus the time for FIQ entry. At the end of this time, the ARM7TDMI will be executing the instruction at 0x1C (FIQ interrupt vector address). The maximum total time is 50 processor cycles, which is just over 1.1S in a system using a continuous 41.78 MHz processor clock. The maximum IRQ latency calculation is similar, but must allow for the fact that FIQ has higher priority and could delay entry into the IRQ handling routine for an arbitrary length of time. This time can be reduced to 42 cycles if the LDM command is not used, some compilers have an option to compile without using this command. Another option is to run the part in THUMB mode where this is reduced to 22 cycles. The minimum latency for FIQ or IRQ interrupts is five cycles in total which consists of the shortest time the request can take through the synchronizer plus the time to enter the exception mode. Note that the ARM7TDMI will always be run in ARM (32-bit) mode when in privileged modes, i.e. when executing interrupt service routines.
00000000h
Figure 25: Physical memory map
Memory Access
The ARM7 core sees memory as a linear array of 232 byte location where the different blocks of memory are mapped as outlined in Figure 25. The ADUC7128 memory organisation is configured in little endian format: the least significant byte is located in the lowest byte address and the most significant byte in the highest byte address.
bit31 Byte3 ... B 7 3 Byte2 Byte1 ... A 6 2 32 bits ... 9 5 1 bit0 Byte0 0xFFFFFFFFh ... 8 4 0
0x00000004h 0x00000000h
Figure 26: little endian format
Rev. PrA | Page 22 of 92
Preliminary Technical Data
Flash/EE Memory
0xFFFF06BC 0xFFFFFFFF 0xFFFF0FBC
ADUC7128
The 128kBytes of Flash/EE are organised as two banks of 32k X 16 bits. In the first block 31k X 16 bits are user space and 1k X 16 bits is reserved for the factory configured boot page.. The page size of this Flash/EE memory is 512Bytes. The second 64kByte block is organized in a similar manner. It is arranged in 32k x 16 bits. All of this is available as user space. 126 kBytes of Flash/EE are available to the user as code and non-volatile data memory. There is no distinction between data and program as ARM code shares the same space. The real width of the Flash/EE memory is 16 bits, which means that in ARM mode (32-bit instruction), two accesses to the Flash/EE are necessary for each instruction fetch. It is therefore recommended to use Thumb mode when executing from Flash/EE memory for optimum access speed. The maximum access speed for the Flash/EE memory is 41.78MHz in Thumb mode and 20.89MHz in full ARM mode. More details on Flash/EE access time are outlined later in `Execution from SRAM and Flash/EE' section of this datasheet.
DDS
0xFFFF0690 0xFFFF0688 0xFFFF0F00 0xFFFF0F18
PW M
DAC
0xFFFF0670 0xFFFF0544 0xFFFF0F00 0xFFFF0EA8
QEN
ADC
0xFFFF0500 0xFFFF04A8 0xFFFF0480 0xFFFF0448 0xFFFF0440 0xFFFF0434 0xFFFF0400 0xFFFF0394 0xFFFF0E80 0xFFFF0E28 0xFFFF0E00 0xFFFF0D70
Flash Control Interface 1 Flash Control Interface 0
Bandgap Reference Power Supply Monitor PLL & Oscillator Control General Purpose Timer 4 Watchdog Timer Wake Up Timer General Purpose Timer
GPIO
0xFFFF0D00 0xFFFF0C30
External Memory
0xFFFF0C00 0xFFFF0B54
PLA
0xFFFF0B00 0xFFFF0A14
0xFFFF0380 0xFFFF0370 0xFFFF0360
SPI
0xFFFF0A00 0xFFFF0948
SRAM
8kBytes of SRAM are available to the user, organized as 2k X 32 bits, i.e. 2kWords. ARM code can run directly from SRAM at 41.78MHz , given that the SRAM array is configured as a 32-bit wide memory array. More details on SRAM access time are outlined later in `Execution from SRAM and Flash/EE' section of this datasheet.
0xFFFF0350 0xFFFF0340 0xFFFF0334 0xFFFF0320 0xFFFF0318
I2 C1
0xFFFF0900 0xFFFF0848
I 2 C0
0xFFFF0800 0xFFFF076C
Timer 0
0xFFFF0300 0xFFFF0240 0xFFFF0740 0xFFFF072C
UART 1
Memory Mapped Registers
The Memory Mapped Register (MMR) space is mapped into the upper 2 pages of the memory array and accessed by indirect addressing through the ARM7 banked registers. The MMR space provides an interface between the CPU and all on-chip peripherals. All registers except the core registers reside in the MMR area. All shaded locations shown in Figure 6 are unoccupied or reserved locations and should not be accessed by user software. Table 8 shows a full MMR memory map. The access time reading or writing a MMR depends on the advanced microcontroller bus architecture (AMBA) bus used to access the peripheral. The processor has two AMBA busses: advanced high performance bus (AHB) used for system modules, and advanced peripheral bus (APB) used for lower performance peripheral. Access to the AHB is one cycle, and access to the APB is two cycles. All peripherals on the ADUC7128 are on the APB except the Flash/EE memory and the GPIOs.
0xFFFF0200 0xFFFF0110 0xFFFF0000
Remap & System Control Interrupt Controller
UART 0
0xFFFF0700 0xFFFF06E8
Figure 27: Memory Mapped
Rev. PrA | Page 23 of 92
ADUC7128
Table 8. Complete MMRs list
Address Name Byte Access Type IRQ address base = 0xFFFF0000 0x0000 0x0004 0x0008 0x000C 0x0010 0x0100 0x0104 0x0108 0x010C 0x0220 0x0230 0x0234 0x0300 0x0304 0x0308 0x030C 0x0310 0x0314 0x0320 0x0324 0x0328 0x032C 0x0330 0x0340 0x0344 0x0348 0x034C 0x0360 0x0364 0x0368 0x036C 0x0380 0x0384 0x0388 IRQSTA IRQSIG IRQEN IRQCLR SWICFG FIQSTA FIQSIG FIQEN FIQCLR REMAP RSTSTA RSTCLR T0LD T0VAL0 T0VAL1 T0CON T0ICLR T0CAP T1LD T1VAL T1CON T1ICLR T1CAP T2LD T2VAL T2CON T2ICLR T3LD T3VAL T3CON T3ICLR T4LD T4VAL T4CON 4 4 4 4 4 4 4 4 4 1 1 1 2 2 4 4 1 2 4 4 4 1 4 4 4 4 1 2 2 2 1 4 4 4 R R RW W W R R RW W RW R W RW R R RW W R RW R RW W R RW R RW W RW R RW W RW R RW 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0x0708
Rev. PrA | Page 24 of 92
Preliminary Technical Data
Address Page Cycle 0x038C 0x0390 0x0404 0x0408 0x040C 0x0410 0x0414 0x0418 Name T4ICLR T4CAP POWKEY1 POWCON POWKEY2 PLLKEY1 PLLCON PLLKEY2 Byte 1 4 2 2 2 2 2 2 Access Type W R W RW W W RW W Cycle 2 2 2 2 2 2 2 2 Page
PLL base address = 0xFFFF0400
PSM address base = 0xFFFF0440 0x0440 0x0444 PSMCON CMPCON 2 2 RW RW 2 2
System Control address base = 0xFFFF0200
Reference address base = 0xFFFF0480 0x048C 0x0500 0x0504 0x0508 0x050C 0x0510 0x0514 0x0530 0x0534 0x0670 0x0690 0x0694 0x0698 0x06A4 0x06B4 0x06B8 0x06BC 0x0700 REFCON ADCCON ADCCP ADCCN ADCSTA ADCDAT ADCRST ADCGN ADCOF DACCON DDSCON DDSFRQ DDSPHS DACKEY0 DACDAT DACEN DACKEY1 COM0TX COM0RX COM0DIV0 0x0704 COM0IEN0 COM0DIV1 COM0IID0 1 2 1 1 1 4 1 2 2 2 1 4 2 1 2 1 1 1 1 1 1 1 1 RW RW RW RW R R W RW RW RW RW RW RW RW RW RW RW RW R RW RW R/W R 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ADC address base = 0xFFFF0500
Timer address base = 0xFFFF0300
DAC and DDS address base = 0xFFFF0670
UART 0 base address = 0xFFFF0700
Preliminary Technical Data
Address Name Byte Access Type 0x070C 0x0710 0x0714 0x0718 0x071C 0x0720 0x0724 0x0728 0X072C
COM0CON0 COM0CON1 COM0STA0 COM0STA1
ADUC7128
Page Address Name Byte Access Type 0x0838 0x083C 0x0840 0x0844 0x0848 0x084C I2C0ID0 I2C0ID1 I2C0ID2 I2C0ID3 I2C0SSC I2C0FIF 1 1 1 1 1 1 RW RW RW RW RW RW Cycle 2 2 2 2 2 2 Page
Cycle 2 2 2 2 2 2 2 2 2
1 1 1 1 1 1 1 1 2
RW RW R R RW RW R RW RW
COM0SCR COM0IEN1 COM0IID1 COM0ADR COM0DIV2
I2C1 base address = 0xFFFF0900 0x0900 0x0904 0x0908 0x090C 0x0910 0x0914 0x0918 0x091C 0x0924 0x0928 0x092C 0x0930 0x0938 0x093C 0x0940 0x0944 0x0948 0x094C 0x0A00 I2C1MSTA I2C1SSTA I2C1SRX I2C1STX I2C1MRX I2C1MTX I2C1CNT I2C1ADR I2C1BYT I2C1ALT I2C1CFG I2C1DIV I2C1ID0 I2C1ID1 I2C1ID2 I2C1ID3 I2C1SSC I2C1FIF SPISTA SPIRX SPITX SPIDIV SPICON PLAELM0 PLAELM1 PLAELM2 PLAELM3 PLAELM4 PLAELM5 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 R R R W R W RW RW RW RW RW RW RW RW RW RW RW RW R R W RW RW RW RW RW RW RW RW 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
UART 1 base address = 0xFFFF0740 0x0740 COM1TX COM1RX COM1DIV0 0x0744 0x0748 0x074C 0x0750 0x0754 0x0758 0x075C 0x0760 0x0764 0x0768 0X076C 0x0800 0x0804 0x0808 0x080C 0x0810 0x0814 0x0818 0x081C 0x0824 0x0828 0x082C 0x0830 COM1IEN0 COM1DIV1 COM1IID0
COM1CON0 COM1CON1 COM1STA0 COM1STA1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 2
RW R RW RW R/W R RW RW R R RW RW R RW RW R R R W R W RW RW RW RW RW RW
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
COM1SCR COM1IEN1 COM1IID1 COM1ADR COM1DIV2 I2C0MSTA I2C0SSTA I2C0SRX I2C0STX I2C0MRX I2C0MTX I2C0CNT I2C0ADR I2C0BYT I2C0ALT I2C0CFG I2C0DIV
SPI base address = 0xFFFF0A00 0x0A04 0x0A08 0x0A0C 0x0A10 0x0B00 0x0B04 0x0B08 0x0B0C 0x0B10 0x0B14
I2C0 base address = 0xFFFF0800
PLA base address = 0xFFFF0B00
Rev. PrA | Page 25 of 92
ADUC7128
Address Name Byte Access Type 0x0B18 0x0B1C 0x0B20 0x0B24 0x0B28 0x0B2C 0x0B30 0x0B34 0x0B38 0x0B3C 0x0B40 0x0B44 0x0B48 0x0B4C 0x0B50 PLAELM6 PLAELM7 PLAELM8 PLAELM9 PLAELM10 PLAELM11 PLAELM12 PLAELM13 PLAELM14 PLAELM15 PLACLK PLAIRQ PLAADC PLADIN PLAOUT 2 2 2 2 2 2 2 2 2 2 1 4 4 4 4 RW RW RW RW RW RW RW RW RW RW RW RW RW RW R Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0x0D68 0x0D6C 0x0E00 0x0E04 0x0E08 0x0E0C 0x0E10 0x0E18 0x0E1C 0x0E20 0x0E80 0x0E84 0x0E88 0x0E8C RW RW RW RW RW RW W W RW RW W W RW RW W W RW W W RW RW W 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0x0E90 0x0E98 0x0E9C 0x0EA0 0x0F00 0x0F04 0x0F08 0x0F0C 0x0F14 0x0F18 Page Address
Preliminary Technical Data
Name Byte Access Type GP4CLR GP4PAR FEE0STA FEE0MOD FEE0CON FEE0DAT FEE0ADR FEE0SGN FEE0PRO FEE0HID FEE1STA FEE1MOD FEE1CON FEE1DAT FEE1ADR FEE1SGN FEE1PRO FEE1HID QENCON QENSTA QENDAT QENVAL QENCLR QENSET
PWMCON1 PWM1COM1 PWM1COM2 PWM1COM3 PWM1LEN PWM2COM1 PWM2COM2 PWM2COM3 PWM2LEN PWM3COM1
Page Cycle 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2
1 1 1 1 1 2 2 3 4 4 1 1 1 2 2 3 4 4 2 1 2 2 1 1
W W R RW RW RW RW R RW RW R RW RW RW RW R RW RW RW R RW R W W
Flash/EE Block 0 base address = 0xFFFF0E00
Flash/EE Block 1 base address = 0xFFFF0E80
GPIO base address = 0xFFFF0D00 0x0D00 0x0D04 0x0D08 0x0D0C 0x0D10 0x0D20 0x0D24 0x0D28 0x0D2C 0x0D30 0x0D34 0x0D38 0x0D3C 0x0D40 0x0D44 0x0D48 0x0D50 0x0D54 0x0D58 0x0D5C 0x0D60 0x0D64 GP0CON GP1CON GP2CON GP3CON GP4CON GP0DAT GP0SET GP0CLR GP0PAR GP1DAT GP1SET GP1CLR GP1PAR GP2DAT GP2SET GP2CLR GP3DAT GP3SET GP3CLR GP3PAR GP4DAT GP4SET 4 4 4 4 4 4 1 1 4 4 1 1 4 4 1 1 4 1 1 4 4 1
QEN base address= 0xFFFF0F00
PWM base address= 0xFFFF0F80 0x0F80 0x0F84 0x0F88 0x0F8C 0x0F90 0x0F94 0x0F98 0x0F9C 0x0FA0 0x0FA4 2 2 2 2 2 2 2 2 2 2 RW RW RW RW RW RW RW RW RW RW 2 2 2 2 2 2 2 2 2 2
Rev. PrA | Page 26 of 92
Preliminary Technical Data
Address Name Byte Access Type 0x0FA8 0x0FAC 0x0FB0 0x0FB4 0x0FB8
PWM3COM2 PWM3COM3 PWM3LEN PWMCON2 PWMICLR
ADUC7128
Page
Cycle 2 2 2 2 2
2 2 2 2 2
RW RW RW RW W
The `Access' column corresponds to the access time reading or writing a MMR. It depends on the AMBA (Advanced Microcontroller Bus Architecture) bus used to access the peripheral. The processor has two AMBA busses, AHB (Advanced High-performance Bus) used for system modules and APB (Advanced Peripheral Bus) used for lower performance peripheral.
Rev. PrA | Page 27 of 92
ADUC7128
ADC CIRCUIT INFORMATION
GENERAL OVERVIEW
The Analog Digital Converter (ADC) incorporates a fast, multichannel, 12-bit ADC. It can operate from 3.0V to 3.6V supplies and is capable of providing a throughput of up to 1MSPS when the clock source is 41.78MHz. This block provides the user with multi-channel multiplexer, differential track-and-hold, on-chip reference and ADC. The ADC consists of a 12-bit successive-approximation converter based around two capacitor DACs. Depending on the input signal configuration, the ADC can operate in one of three different modes 1. 2. 3. Fully differential mode, for small and balanced signals. Single-ended mode, for any single-ended signals. Pseudo differential mode, for any single-ended signals, taking advantage of the common mode rejection offered by the pseudo differential input.
Preliminary Technical Data
temperature sensor channel, measuring die temperature to an accuracy of 3C.
ADC TRANSFER FUNCTION
Pseudo-differential and single-ended modes
In pseudo-differential or single-ended mode, the input range is 0 V to VREF. The output coding is straight binary in pseudo differential and single-ended modes with: 1 LSB = FS/4096 or 2.5 V/4096 = 0.61 mV or 610 V when VBREFB = 2.5 V The ideal code transitions occur midway between successive integer LSB values (i.e. 1/2 LSB, 3/2 LSBs, 5/2 LSBs, . . ., FS -3/2 LSBs). The ideal input/output transfer characteristic is shown in Figure 29.
OUTPUT CODE 1111 1111 1111 1111 1111 1110 1111 1111 1101
The converter accepts an analog input range of 0 to VREF when operating in single-ended mode or pseudo-differential mode. In fully differential mode, the input signal must be balanced around a common mode voltage VCM, in the range 0V to AVDD and with a maximum amplitude of 2 VREF (see Figure 28).
AVDD VCM VCM 2VREF 2VREF
1111 1111 1100
1LSB =
FS 4096
0000 0000 0011 0000 0000 0010 0000 0000 0001 0000 0000 0000 0V 1LSB VOLTAGE INPUT +FS - 1LSB
Figure 29: ADC transfer function in pseudo differential mode or single-ended mode
VCM 0 2VREF
Fully differential mode
The amplitude of the differential signal is the difference between the signals applied to the VIN+ and VIN- pins (i.e., VIN+ - VIN-). The maximum amplitude of the differential signal is therefore -VREF to +VREF p-p (i.e. 2 X VREF). This is regardless of the common mode (CM). The common mode is the average of the two signals, i.e. (VIN+ + VIN-)/2 and is therefore the voltage that the two inputs are centred on. This results in the span of each input being CM VREF/2. This voltage has to be set up externally and its range varies with VREF, (see driving the ADC). The output coding is two's complement in fully differential mode with 1 LSB = 2VREF/4096 or 2x2.5 V/4096 = 1.22 mV when VREF = 2.5 V. The output result is +/- 11 bits but this is shifted by one to the right. This allows the result in ADCDAT to be declared as a signed integer when writing `c' code. The designed code transitions occur midway between successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs, . . ., FS -3/2 LSBs). The ideal input/output transfer characteristic is shown in Figure 30.
Figure 28: examples of balanced signals for fully differential mode
A high precision, low drift, and factory calibrated 2.5 V reference is provided on-chip. An external reference can also be connected as described later in the Bandgap Reference section. Single or continuous conversion modes can be initiated in software. An external START pin, an output generated from the on-chip PLA or a Timer0 or a Timer1 overflow can also be used to generate a repetitive trigger for ADC conversions.
E ACONV EA
If the signal has not been de asserted by the time the ADC conversion is complete then a second conversion will begin automatically. A voltage output from proportional to absolute through the front end additional ADC channel an on-chip bandgap reference temperature can also be routed ADC multiplexer, effectively an input. This facilitates an internal
Rev. PrA | Page 28 of 92
Preliminary Technical Data
ACQ BIT TRIAL
ADUC7128
WRITE
SIGN BIT
OUTPUT CODE 0 1111 1111 1110
ADC CLOCK
0 1111 1111 1100 0 1111 1111 1010
1LSB =
2xV REF 4096
CONVTSTART
0 0000 0000 0001 0 0000 0000 0000 1 1111 1111 1110
ADCDAT DATA ADCBUSY
1 0000 0000 0100 1 0000 0000 0010 1 0000 0000 0000 -V REF + 1LSB 0LSB +V REF - 1LSB
ADC INTERRUPT ADCSTA = 0 ADCSTA = 1
04955-015
VOLTAGE INPUT (Vin+ - Vin-)
Figure 32. ADC Timing
Figure 30: ADC transfer function in differential mode
ADC MMRS interface
The ADC is controlled and configured via a number of MMRs that are listed below and described in detail in the following pages: - ADCCON: ADC Control Register allows the programmer to enable the ADC peripheral, to select the mode of operation of the ADC, either Single-ended, pseudo-differential or fully differential mode and the conversion type. This MMR is described Table 9. - ADCCP: ADC positive Channel selection Register - ADCCN: ADC negative Channel selection Register ADCSTA: ADC Status Register, indicates when an ADC 0 conversion result is ready. The ADCSTA register contains only one bit, ADCReady, bit (bit 0), representing the status of the ADC. This bit is set at the end of an ADC conversion generating an ADC interrupt, it is cleared automatically by reading the ADCDAT MMR. When the ADC is performing a conversion, the status of the ADC can be read externally via the ADCBusy pin. This pin is high during a conversion. When the conversion is finished, ADCBusy goes back low. This information can be available on P0.5 (see chapter on GPIO) if enabled in GP0CON register. ADCDAT: ADC Data Result Register, hold the 12-bit ADC result as shown Figure 31 - ADCRST: ADC Reset Register. Resets all the ADC registers to their default value.
TYPICAL OPERATION
Once configured via the ADC control and channel selection registers, the ADC will convert the analog input and provide a 11-bit result in the ADC data register. The top 4 bits are the sign bits and the 11-bit result is placed from bit 16 to 27 as shown in Figure 31. Again, it should be noted that in fully differential mode, the result is represented in two's complement format shifted one bit to the right , and in pseudo differential and single-ended mode, the result is represented in straight binary format.
31 27 16 15
SIGN BITS
12-bit ADC RESULT
Figure 31: ADC Result Format
Timing
Figure 32 gives details of the ADC timing. Users have control on the ADC clock speed and on the number of acquisition clock in the ADCCON MMR. By default, the acquisition time is eight clocks and the clock divider is two. The number of extra clocks (such as bit trial or write) is set to 19, which gives a sampling rate of 819 kSPS. For conversion on temperature sensor, the ADC acquisition time is automatically set to 16 clocks and the ADC clock divider to 32.
Rev. PrA | Page 29 of 92
ADUC7128
Table 9: ADCCON MMR Bit Designations Bit 1210 Description ADC Speed (Fadc = Fcore, conversion = 14 ADC clocks + Acquisition time) 000 - Fadc / 1 001 - Fadc / 2 010 - Fadc / 4 011 - Fadc / 8 100 - Fadc / 16 101 - Fadc / 32 9-8 ADC Acquisition Time (number of ADC clocks) 00 - 2 01 - 4 10 - 8 11 - 16 7 Enable Conversion Set by the user to enable conversion mode Cleared by the user to disable conversion mode 6 Reserved This bit should be set to 0 by the user. 5 ADC power control:
Preliminary Technical Data
Set by the user to place the ADC in normal mode, the ADC must be powered up for at least 500uS before it will convert correctly. Cleared by the user to place the ADC in power-down mode 4-3 Conversion Mode: 00 01 10 11 2-0 Single Ended Mode Differential Mode Pseudo-Differential Mode Reserved
Conversion Type: 000 001 010 011 Enable CONVBSTARTB pin as a conversion input Enable timer 1 as a conversion input Enable timer 0 as a conversion input Single software conversion, will be set to 000 after conversion. (Bit 7 of ADCCON MMR should be cleared after starting a single software conversion to avoid further conversions triggered by the CONVSTART pin).
Rev. PrA | Page 30 of 92
Preliminary Technical Data
100 101 110 Other Continuous software conversion PLA conversion PWM conversion Reserved
ADUC7128
Table 10: ADCCP* MMR bit designation Bit 7-5 4-0 Description Reserved Positive Channel Selection Bits 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 Others ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10 ADC11 ADC12/LD2TX ADC13/LD1TX Reserved Reserved Temperature sensor AGND Reference AVDD/2 Reserved Bit 7-5 4-0
Table 11: ADCCN* MMR bit designation Description Reserved Negative Channel Selection Bits 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 Others ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10 ADC11 ADC12/LD2TX ADC13/LD1TX Reserved Reserved Temperature sensor Reserved
* ADC channel availability depends on part model.
Since ADC12 and ADC13 are shared with the Line Driver TX pins a high level of crosstalk will be seen on these pins when used in ADC mode.
Rev. PrA | Page 31 of 92
ADUC7128
CONVERTER OPERATION
The ADC incorporates a successive approximation (SAR) architecture involving a charge-sampled input stage. This architecture is described below for the three different modes of operation.
Preliminary Technical Data
Pseudo-differential mode
In pseudo-differential mode, Channel- is linked to the VIN- pin of the ADUC7128 and SW2 switches between A (Channel-) and B (VREF). VIN- pin must be connected to Ground or a low voltage. The input signal on VIN+ can then vary from VIN- to VREF + VIN-. Note VIN- must be chosen so that VREF + VIN- does not exceed AVBDDB.
AIN0 CAPACITIVE DAC COMPARATOR CONTROL LOGIC
Differential mode
The ADUC7128 contains a successive approximation ADC based on two capacitive DACs. Figure 33 and Figure 34 show simplified schematics of the ADC in acquisition and conversion phase, respectively. The ADC is comprised of control logic, a SAR, and two capacitive DACs. In Figure 33 (the acquisition phase), SW3 is closed and SW1 and SW2 are in Position A, the comparator is held in a balanced condition, and the sampling capacitor arrays acquire the differential signal on the input.
CAPACITIVE DAC AIN0 Channel+ B A SW1 A SW2 ChannelAIN11 B VREF Cs Cs COMPARATOR CONTROL LOGIC
...
MUX
Channel+
B A SW1 A SW2 B VREF
Cs
SW3 Cs
AIN11
VINChannel-
CAPACITIVE DAC
Figure 35: ADC in pseudo-differential mode
Single-ended mode
In Single-ended mode, SW2 is always connected internally to ground. The VIN- pin can be floating. The input signal range on VIN+ is 0V to VREF.
AIN0 CAPACITIVE DAC COMPARATOR CONTROL LOGIC
...
MUX
SW3
CAPACITIVE DAC
...
Figure 33: ADC acquisition phase
When the ADC starts a conversion (Figure 34), SW3 will open and SW1 and SW2 will move to Position B, causing the comparator to become unbalanced. Both inputs are disconnected once the conversion begins. The control logic and the charge redistribution DACs are used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC's output code. The output impedances of the sources driving the VIN+ and VIN- pins must be matched; otherwise, the two inputs will have different settling times, resulting in errors.
CAPACITIVE DAC AIN0 Channel+ B A SW1 A SW2 B VREF Cs COMPARATOR CONTROL LOGIC
MUX
Channel+
B A SW1 Channel-
Cs
SW3 Cs
AIN11
VIN-
CAPACITIVE DAC
Figure 36: ADC in single-ended mode
Analog Input Structure
Figure 37 shows the equivalent circuit of the analog input structure of the ADC. The four diodes provides ESD protection for the analog inputs. Care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300 mV. This would cause these diodes to become forward biased and start conducting into the substrate. These diodes can conduct up to 10 mA without causing irreversible damage to the part. The capacitors C1 in Figure 37 are typically 4 pF and can primarily be attributed to pin capacitance. The resistors are lumped components made up of the ON resistance of the switches. The value of these resistors is typically about 100 . The capacitors, C2, are the ADC's sampling capacitors and have a capacitance of 16 pF typically.
...
MUX Channel-
SW3 Cs
AIN11 CAPACITIVE DAC
Figure 34: ADC conversion phase
Rev. PrA | Page 32 of 92
Preliminary Technical Data
AVDD D R1 C2
ADUC7128
THD will increase as the source impedance increases and the performance will degrade.
DRIVING THE ANALOG INPUTS
Internal or external reference can be used for the ADC. In differential mode of operation, there are restrictions on common mode input signal (VBCMB) that are dependant on reference value and supply voltage used to ensure that the signal remains within the supply rails. Table 12 gives some calculated VBCMB min VBCMB max for some conditions. Table 12: VBCMB ranges
C1
D
AVDD D R1 C2
C1
D
Figure 37: Equivalent Analog Input Circuit Conversion Phase: Switches Open Track Phase: Switches Closed
AVDD 3.3V
VREF 2.5V 2.048V
VBCMB min 1.25V 1.024V 0.75V 1.25V 1.024V 0.75V
VBCMB max 2.05V 2.276V 2.55V 1.75V 1.976V 2.25V
Signal Peak-Peak 2.5V 2.048V 1.25 2.5V 2.048V 1.25
For AC applications, removing high-frequency components from the analog input signal is recommended by the use of an RC low-pass filter on the relevant analog input pins. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances will significantly affect the AC performance of the ADC. This may necessitate the use of an input buffer amplifier. The choice of the op amp will be a function of the particular application. Figure 38 and Figure 39 give an example of ADC front end.
ADuC7229
1.25 3.0V 2.5V 2.048V 1.25
TEMPERATURE SENSOR
The ADUC7128 provides a voltage output from an on-chip bandgap reference proportional to absolute temperature. It can also be routed through the front end ADC multiplexer (effectively an additional ADC channel input) facilitating an internal temperature sensor channel, measuring die temperature to an accuracy of 3C.
10 0.01 F
ADC0
BANDGAP REFERENCE
The ADUC7128 provides an on-chip bandgap reference of 2.5V, which can be used for the ADC and for the DAC. This internal reference also appears on the VBREFB pin. When using the internal reference, a capacitor of 0.47F must be connected from the external VBREFB pin to AGND, to ensure stability and fast response during ADC conversions. This reference can also be connected to an external pin (VREF) and used as a reference for other circuits in the system. An external buffer would be required because of the low drive capability of the VREF output. A programmable option also allows an external reference input on the VBREFB pin. The bandgap reference interface consists on a 8-bit MMR, REFCON described in the following table.
Figure 38. Buffering Single-Ended/Pseudo Differential Input
ADuC7229 ADC0 Vref ADC1
Figure 39. Buffering Differential Inputs
When no amplifier is used to drive the analog input, the source impedance should be limited to values lower than 1 k . The maximum source impedance will depend on the amount of total harmonic distortion (THD) that can be tolerated. The
Rev. PrA | Page 33 of 92
ADUC7128
Table 13: REFCON MMR bit designations Bit 7-2 1 Description Reserved Internal reference powerdown enable Set by user to place the internal reference in powerdown mode and use an external reference Cleared by user to place the internal reference in normal mode and use it for ADC conversions Internal reference output enable Set by user to connect the internal 2.5V reference to the VREF pin. The reference can be used for external component but will need to be buffered. Cleared by user to disconnect the reference from the VREF pin. Note: The on chip DAC is only functional with the internal reference output enable bit set. It will not work with an external reference.
Preliminary Technical Data
0
Rev. PrA | Page 34 of 92
Preliminary Technical Data
NONVOLATILE FLASH/EE MEMORY
HT TH
ADUC7128
code download and debug. An application note is available at www.analog.com/microconverterU describing the protocol via JTAG. It is possible to write to a single Flash/EE location address twice. If a single address is written to more than twice, then the data within the Flash/EE memory could be corrupted. That is, it is possible to walk zeros only byte wise.
FLASH/EE MEMORY OVERVIEW
The ADUC7128 incorporates Flash/EE memory technology onchip to provide the user with non-volatile, in-circuit reprogrammable memory space. Like EEPROM, Flash memory can be programmed in-system at a byte level, although it must first be erased. The erase is performed in page blocks. As a result, flash memory is often and more correctly referred to as Flash/EE memory. Overall, Flash/EE memory represents a step closer to the ideal memory device that includes non-volatility, in-circuit programmability, high density, and low cost. Incorporated in the ADUC7128, Flash/EE memory technology allows the user to update program code space in-circuit, without the need to replace one time programmable (OTP) devices at remote operating nodes.
FLASH/EE MEMORY SECURITY
The 126 kB of Flash/EE memory available to the user can be read and write protected. Bit 31 of the FEE0PRO/FEE0HID MMR protects the 126 kB from being read through JTAG and also in parallel programming mode. The other 31 bits of this register protect writing to the flash memory; each bit protects 4 pages, that is, 2 kB. Write protection is activated for all type of access. FEE1PRO and FEE1HID similarly protect the second 64kB block. All 32 bits of this are used to protect 4 pages at a time.
FLASH/EE MEMORY AND THE ADUC7128
The ADUC7128 contains two 64 kByte arrays of Flash/EE Memory. In the first block the lower 62 Kbytes is available to the user and the upper 2 kBytes of this Flash/EE program memory array contain permanently embedded firmware, allowing in circuit serial download. These 2 Kbytes of embedded firmware also contain a power-on configuration routine that downloads factory calibrated coefficients to the various calibrated peripherals (bandgap references and so on). This 2 kByte embedded firmware is hidden from user code. It is not possible for the user to read, write or erase this page. In the second block all 64kB of Flash/EE memory are available to the user. The 126kBytes of Flash/EE memory can be programmed incircuit, using the serial download mode or the JTAG mode provided. 1. 2.
Three Levels of Protection
Protection can be set and removed by writing directly into FEExHID MMR. This protection does not remain after reset. Protection can be set by writing into FEExPRO MMR. It only takes effect after a save protection command (0x0C) and a reset. The FEExPRO MMR is protected by a key to avoid direct access. The key is saved once and must be entered again to modify FEExPRO. A mass erase sets the key back to 0xFFFF but also erases all the user code. The Flash can be permanently protected by using the FEEPRO MMR and a particular value of key: 0xDEADDEAD. Entering the key again to modify the FEExPRO register is not allowed
3.
(1) Serial Downloading (In-Circuit Programming)
The ADUC7128 facilitates code download via the standard UART serial port or via the I2C port. The ADUC7128 enters serial download mode after a reset or power cycle if the BM pin is pulled low through an external 1kOhm resistor. Once in serial download mode, the user can download code to the full 126kBytes of Flash/EE memory while the device is in circuit in its target application hardware. A PC serial download executable is provided as part of the development system for serial downloading via the UART. An application note is available at www.analog.com/microconverterU describing the protocol for serial downloading via the UART and I2C.
HTU TH
Sequence to Write the Key
1. 2. 3. 4. 5. Write the bit in FEExPRO corresponding to the page to be protected. Enable key protection by setting Bit 6 of FEExMOD (Bit 5 must be = 0). Write a 32-bit key in FEExADR, FEExDAT. Run the write key command 0x0C in FEExCON; wait for the read to be successful by monitoring FEExSTA. Reset the part.
(2) JTAG access
The JTAG protocol uses the on-chip JTAG interface to facilitate
To remove or modify the protection, the same sequence is used with a modified value of FEExPRO. If the key chosen is the value 0xDEAD, then the memory protection cannot be removed. Only a mass erase unprotects the part, but it also
Rev. PrA | Page 35 of 92
ADUC7128
erases all user code. The sequence to write the key is illustrated in the following example; this protects writing pages 4 to 7 of the Flash:
Name FEE1DAT
Preliminary Technical Data
FEE1DAT Register
Address 0xFFFF0E8C Default Value 0xXXXX Access RW
FEE0PRO=0xFFFFFFFD; to 7 FEE0MOD=0x48; FEE0ADR=0x1234; FEE0DAT=0x5678; FEE0CON= 0x0C; command
//Protect pages 4 //Write key enable //16 bit key value //16 bit key value // Write key
FEE1DAT is a 16-bit data register.
FEE1ADR Register
Name FEE1ADR Address 0xFFFF0E90 Default Value 0x0000 Access RW
FEE1ADR is another 16-bit address register.
The same sequence should be followed to protect the part permanently with FEEADR = 0xDEAD and FEEDAT = 0xDEADT.
T
FEE1SGN Register
Name FEE1SGN Address 0xFFFF0E98 Default Value 0xFFFFFF Access R
FLASH/EE CONTROL INTERFACE
FEE0DAT Register
Name FEE0DAT Address 0xFFFF0E0C Default Value 0xXXXX Access RW
FEE1SGN is a 24-bit code signature.
FEE1PRO Register
Name FEE1PRO Address 0xFFFF0E9C Default Value 0x00000000 Access RW
FEE0DAT is a 16-bit data register.
FEE1PRO provides immediate protection MMR. It does not require any software keys. See description in Table 17.
Access RW
FEE0ADR Register
Name FEE0ADR Address 0xFFFF0E10 Default Value 0x0000
FEE1HID Register
Name FEE1HID Address 0xFFFF0EA0 Default Value 0xFFFFFFFF Access RW
FEE0ADR is another 16-bit address register.
FEE0SGN Register
Name FEE0SGN Address 0xFFFF0E18 Default Value 0xFFFFFF Access R
FEE1HID provides protection following subsequent reset MMR. It requires a software key. See description in Table 18.
FEE0SGN is a 24-bit code signature.
FEE0PRO Register
Name FEE0PRO Address 0xFFFF0E1C Default Value 0x00000000 Access RW
FEE0PRO provides immediate protection MMR. It does not require any software keys. See description in Table 17.
FEE0HID Register
Name FEE0HID Address 0xFFFF0E20 Default Value 0xFFFFFFFF Access RW
FEE0HID provides protection following subsequent reset MMR. It requires a software key. See description in Table 18.
Command Sequence for Executing a Mass Erase
FEE0DAT=0x3CFF; FEE0ADR = 0xFFC3; FEE0MOD= FEE0MOD|0x8; //Erase key enable FEE0CON=0x06; //Mass erase command
Rev. PrA | Page 36 of 92
Preliminary Technical Data
Table 14: FEExSTA MMR bit designations Bit 15-6 5 4 3 Description Reserved Burst command enable Set when the command is a burst command: 0x07, 0x08 or 0x09 Cleared when other command Reserved
ADUC7128
2 1 0
Flash interrupt status bit Set automatically when an interrupt occurs, i.e. when a command is complete and the Flash/EE interrupt enable bit in the FEExMOD register is set Cleared when reading FEExSTA register Flash/EE controller busy Set automatically when the controller is busy Cleared automatically when the controller is not busy Command fail Set automatically when a command completes unsuccessfully Cleared automatically when reading FEExSTA register Command complete Set by MicroConverter when a command is complete Cleared automatically when reading FEExSTA register
Table 15: FEExMOD MMR bit designations Bit 7-5 4 Description Reserved Flash/EE interrupt enable: Set by user to enable the Flash/EE interrupt. The interrupt will occur when a command is complete. Cleared by user to disable the Flash/EE interrupt
Erase/write command protection. Set by user to enable the erase and write commands. Clear to protect the Flash against erase/write command.
3
2 1-0
Reserved Flash waitstates, when the kernel exits this with be set to 1. The user should first switch to the external 32kHz crystal before setting the waitstates to 0. Both flash blocks must have the same wait state value for any change to take effect.
Table 16: command codes in FEExCON Code 0x00T* 0x01* 0x02* 0x03*
P PT
command Null Single Read Single Write Erase-Write Single Verify Single Erase Mass erase Burst read Burst readwrite Erase Burst read-write
0x04* 0x05* 0x06* 0x07 0x08 0x09
Description Idle state Load FEExDAT with the 16-bit data indexed by FEExADR Write FEExDAT at the address pointed by FEExADR. This operation takes 20s. Erase the page indexed by FEExADR and write FEExDAT at the location pointed by FEExADR. This operation takes 20ms Compare the contents of the location pointed by FEExADR to the data in FEExDAT. The result of the comparison is returned in FEExSTA bit 1 Erase the page indexed by FEExADR Erase user space. The 2kByte of kernel are protected in block 0. This operation takes 2.48s To prevent accidental execution a command sequence is required to execute this instruction, this is described below. Default command. No write is allowed. This operation takes 2 cycles Write can handle a maximum of 8 data of 16 bits and takes a maximum of 8 x 20 s Will automatically erase the page indexed by the write, allow to write pages without running an erase command. This command takes 20 ms to erase the page + 20 s per data to write
Rev. PrA | Page 37 of 92
ADUC7128
0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
*
TP PT
Preliminary Technical Data
Stops the running burst to allow execution from Flash/EE immediately Give a signature of the 64kBytes of Flash/EE in the 24-bit FEExSIGN MMR. This operation takes 32778 clock cycles. This command can be run only once. The value of FEExPRO is saved and can be removed only with a mass erase (0x06) or with the key Reserved Reserved No operation, interrupt generated
Burst termination Signature Protect Reserved Reserved Ping
The FEExCON will always read 0x07 immediately after execution of any of these commands.
Table 17: FEE0PRO and FEE0HID MMR bit designations Bit 31 30-0 Description Read protection Cleared by user to protect block 0. Set by user to allow reading block 0. Write protection for pages 123 to 120, for pages 119 to 116... and for pages 0 to 3 Cleared by user to protect the pages in writing Set by user to allow writing the pages Table 18: FEE1PRO and FEE1HID MMR bit designations Bit 31 30 31-0 Description Read protection Cleared by user to protect block 1. Set by user to allow reading block 1. Write Protection for pages 127 to 120 Cleared by user to protect the pages in writing Set by user to allow writing the pages Write protection for pages for pages 119 to 116... and for pages 0 to 3 Cleared by user to protect the pages in writing Set by user to allow writing the pages
Rev. PrA | Page 38 of 92
Preliminary Technical Data
Execution time from SRAM and FLASH/EE
This chapter describes SRAM and Flash/EE access times during execution for applications where execution time is critical.
ADUC7128
that involve using the Flash/EE for data memory. If the instruction to be executed is a control flow instruction, an extra cycle is needed to decode the new address of the program counter and then four cycles are needed to fill the pipe-line. A data processing instruction involving only core register doesn't require any extra clock cycle but if it involves data in Flash/EE, an extra clock cycle is needed to decode the address of the data and two cycles to get the 32-bit data from Flash/EE. An extra cycle must also be added before fetching another instruction. Data transfer instruction are more complex and are summarised Table 19. Table 19: execution cycles in ARM/Thumb mode Instructions LD LDH LDM/PUSH STR STRH STRM/POP Fetch cycles 2/1 2/1 2/1 2/1 2/1 2/1 Dead time 1 1 N 1 1 N Data access 2 1 2xn 2 x 20s 20s 2 x N x 20s Dead time 1 1 N 1 1 N
Execution from SRAM
Fetching instructions from SRAM takes one clock cycle as the access time of the SRAM is 2ns and a clock cycle is 23ns minimum. However, if the instruction involve reading or writing data to memory, one extra cycle must be added if the data is in SRAM, or three cycle if the data is in Flash/EE, one cycle to execute the instruction and two cycles to get the 32-bit data from Flash/EE. A control flow instruction, for example a branch instruction will take one cycle to fetch but also two cycle to fill the pipeline with the new instructions.
Execution from Flash/EE
Because the Flash/EE width is 16-bit and access time for 16-bit words is 23ns, execution from Flash/EE cannot be done in one cycle as from SRAM when CD bit =0. Also some dead times are needed before accessing data for any value of CD bits. In ARM mode, where instructions are 32 bits, two cycles are needed to fetch any instruction when CD = 0 and in Thumb mode, where instructions are 16 bits, one cycle is needed to fetch any instruction. Timing is identical in both mode when executing instructions
With 1Rev. PrA | Page 39 of 92
ADUC7128
RESET AND REMAP
The ARM exception vectors are all situated at the bottom of the memory array, from address 0x00000000 to address 0x00000020 as shown Figure 40.
Preliminary Technical Data
Remap operation
When a reset occurs on the ADUC7128, execution starts automatically in factory programmed internal configuration code. This so called kernel is hidden and cannot be accessed by user code. If the ADUC7128 is in normal mode (BM pin is high), it will execute the power-on configuration routine of the kernel and then jump to the reset vector address, 0x00000000, to execute the users reset exception routine. Because the Flash/EE is mirrored at the bottom of the memory array at reset, the reset interrupt routine must always be written in Flash/EE. The remap is done from Flash/EE by setting bit0 of the REMAP register. Precaution must be taken to execute this command from Flash/EE, above address 0x00080020, and not from the bottom of the array as this will be replaced by the SRAM. This operation is reversible: the Flash/EE can be remapped at address 0x00000000 by clearing Bit0 of the REMAP MMR. Precaution must again be taken to execute the remap function from outside the mirrored area. Any kind of reset will remap the Flash /EE memory at the bottom of the array.
FFFFFFFFh
kernel interrupt service routines
0008FFFFh
Flash/EE
00080000h
00041FFFh interrupt service routines 00040000h
SRAM
Mirror Space
ARM exception 0x00000020 00000000h vector addresses 0x00000000
Figure 40: remap for exception execution
By default and after any reset, the Flash/EE is mirrored at the bottom of the memory array. The remap function allows the programmer to mirror the SRAM at the bottom of the memory array, facilitating execution of exception routines from SRAM instead of from Flash/EE. This means exceptions are executed twice as fast, exception being executed in ARM mode (32 bit) and the SRAM being 32-bit wide instead of 16-bit wide Flash/EE memory.
Reset
There are four kinds of reset: external reset, Power-on-reset, watchdog expiation and software force. The RSTSTA register indicates the source of the last reset and RSTCLR allows to clear the RSTSTA register. These registers can be used during a reset exception service routine to identify the source of the reset. If RSTSTA is null, the reset was external. Note: When clearing RSTSTA all bits that are currently `1' must be cleared, otherwise a reset event will occur.
Table 20: REMAP MMR bit designations Bit 0 Name Remap Description Remap Bit. Set by the user to remap the SRAM to address 0x00000000. Cleared automatically after reset to remap the Flash/EE memory to address 0x00000000. Table 21: RSTSTA MMR bit designations Bit 7-3 2 1 0 Description Reserved Software reset Set by user to force a software reset. Cleared by setting the corresponding bit in RSTCLR Watchdog timeout Set automatically when a watchdog timeout occurs Cleared by setting the corresponding bit in RSTCLR Power-on-reset Set automatically when a power-on-reset occurs Cleared by setting the corresponding bit in RSTCLR
Rev. PrA | Page 40 of 92
Preliminary Technical Data
OTHER ANALOG PERIPHERALS
DAC
ADUC7128
The ADUC7128 features a 10-bit current DAC which can be used to generate user defined waveforms or sine waves generated by the DDS. The DAC consists of a 10 bit IDAC followed by a current to voltage conversion. The current output of the IDAC is passed through a resistor and capacitor network where it is both filtered and converted to a voltage. This voltage is then buffered by an op-amp and passed to the line driver. The user may optionally disable the internal filter and place an external filter between VDAC and AIN5. For the DAC to function the internal 2.5v voltage reference must be enabled and driven out onto an external capacitor, i.e. REFCON = 0x01. Once the DAC is enabled users will see a 5mV drop in the internal reference value. This is due to bias currents drawn from the reference used in the DAC circuitry. It is recommended that if using the DAC then it is left powered on to avoid seeing variations in ADC results. Table 22: DACCON MMR bit designations Bit 10-9 Description 00 01 10 11 8 7 6 5 4 Shuffle one increment at a time. Shuffle based on an internal counter. Shuffle based on the input data. Reserved.
3 2-1
MSB Shuffle Enable Control Set by user to enable MSB Shuffling Cleared by user to disable MSB Shuffling LSB Shuffle Enable Control Set by user to enable LSB Shuffling Cleared by user to disable LSB Shuffling Power Reduction Control Set by user to reduce power consumption of DAC and line driver, this will also reduce the performance of the circuit. Cleared by user to operate in normal power mode. Output Enable. This bit operates is all modes Set by user to enable the Line Drive output. Cleared by user to disable the Line Driver output. In this mode the line driver output is high impedance. Single ended or Differential output Control. Set by user to operated in differential mode, the output is the differential voltage between LD1TX and LD2TX The voltage output range will be Vref/2 +/- Vref/2 Cleared by user to reference the LD1TX output to AGND The voltage output rage will be AVdd/2 +/- Vref/2 Reserved, This bit should be set to `0' by the user. Operation Mode Control. This bit selects the mode of operation of the DAC. 00 Powerdown 01 Reserved 10 Reserved 11 DDS and DAC mode, selected by DACEN DAC update rate control This bit has no effect when in DDS or PLM mode. Set by user to update the DAC on the negative edge of Timer 1. This allows the user to use any one of the core clk, osc clk, baud clks or user clk and divide these down by 1, 16, 256 or 32768. A user can do waveform generation by writing to the Dac Data Register from ram and update the dac at regular intervals via timer1. Cleared by user to update the DAC on the negative edge of HCLK.
0
Rev. PrA | Page 41 of 92
ADUC7128
DACEN Register
Name DACEN Bit 7 to 1 0 Address 0xFFFF06B8 Default Value 0x00
Preliminary Technical Data
Access RW
DACEN MMR Bit Designations
Description Reserved. Set to `1' by the user to enable DAC mode Set to `0' by the user to enable DDS mode
DACDAT Register
Name DACDAT Bit 15 to 10 9 to 0 Address 0xFFFF06B4 Description Reserved. 10-bit data for DAC Default Value 0x0000 Access RW
Table 23. DACDAT MMR Bit Designations
The DACDAT MMR controls the output of the DAC. The data written to this register is a +/- 9 bits signed value. This means that 0x0000 represents midscale, 0x0200 represents zero scale and 0x01FF full scale. DACEN and DACDAT require key access, the write to these MMRs follow the sequence below,
DACEN DACKEY0 = 0x07 DACEN = User Value DACKEY1 = 0xB9 DACDAT DACKEY0 = 0x07 DACDAT = User Value DACKEY1 = 0xB9
Rev. PrA | Page 42 of 92
Preliminary Technical Data
DDS
ADUC7128
The DDS is used to generate a digital sine wave signal for the DAC on the ADUC7128. It can be enabled into a free running mode by the user. Both the phase and frequency can be controlled. Table 24: DDSCON MMR bit designations Bit 7-6 5 4 0 Description Reserved DDS Output Enable Set by user to enable the DDS output, this only has effect if the DDS is selected in DACCON Cleared by user to disable the DDS output. Reserved Binary Divide Control. DIV Scale Ratio 0000 0001 0010 0011 0100 0101 0110 0111 1xxx 0.000 0.125 0.250 0.375 0.500 0.625 0.750 0.875 1.000
DDSFRQ Register
Name DDSFRQ Bit 31 to 0 Address 0xFFFF0694 Description FSW Default Value 0x00000000 Access RW
Table 25. DACDAT MMR Bit Designations
The DDS Frequency is controlled via the DDSFRQ MMR. This MMR contains a 32 bit word (FSW, frequency select word) which controls the frequency according to the following formula:
Frequency =
FSW x 20.8896MHz 2 32
Address 0xFFFF0698 Description Reserved. Phase Default Value 0x00000000 Access RW
DDSPHS Register
Name DDSPHS Bit 31 to 12 11 to 0
Table 26. DDSPHS MMR Bit Designations
Rev. PrA | Page 43 of 92
ADUC7128
Preliminary Technical Data
The DDS Phase offset is controlled via the DDSPHS MMR. This MMR contains a 12 bit value which controls the phase of the DDS output according to the following formula:
Phaseoffset =
2 x x Phase 212
Rev. PrA | Page 44 of 92
Preliminary Technical Data
ADUC7128
POWER SUPPLY MONITOR
The Power Supply Monitor monitors the IOVDD supply on the ADUC7128. It indicate when IOVBDDB supply pin drops below one of two supply trip points. The monitor function is controlled via the PSMCON register. If enabled in the IRQEN or FIQEN register, the monitor will interrupt the core using the PSMI bit in the PSMCON MMR. This bit will be cleared immediately once CMP goes high. Note that if the interrupt generated is exited before CMP goes high (i.e. IOVdd above the trip point) then no further interrupts will be generated until CMP returns high. The user should ensure that code execution remains within the ISR until CMP returns high. This monitor function allows the user to save working registers to avoid possible data loss due to the low supply or brown-out conditions, and also ensures that normal code execution will not resume until a safe supply level has been established. The PSM will not operate correctly when using JTAG debug. It should be disabled in this mode.
Table 27: PSMCON MMR bit descriptions Bit 3 Name CMP Description Comparator Bit This is a read-only bit and directly reflects the state of the comparator Read `1' indicates the IOVBDDB supply is above its selected trip point. Read `0' indicates the IOVBDDB supply is below its selected trip point. Trip Point Selection Bits 0 - 2.79V 1 - 3.07V Power Supply Monitor Enable Bit Set to `1' by the user to enable the Power Supply Monitor circuit Clear to `0' by the user to disable the Power Supply Monitor circuit Power Supply Monitor Interrupt Bit. This bit will be set high by the MicroConverter if CMP is low, indicating low I/O supply. The PSMI Bit can be used to interrupt the processor. Once CMP returns high, the PSMI bit may be cleared by writing a `1' to this location. A write of `0' has no effect. There is no timeout delay, PSMI may be cleared immediately once CMP goes high.
2
TP
1
PSMEN
0
PSMI
Rev. PrA | Page 45 of 92
ADUC7128
COMPARATOR
The ADUC7128 also integrates an uncommitted voltage comparator. The positive input is multiplexed with ADC2 and the negative input has two options: ADC3 or the internal reference. The output of the comparator can be configured to generate a system interrupt, can be routed directly to the Programmable Logic Array, can start an ADC conversion or be on an external pin, CMPBOUTB.
Preliminary Technical Data
COMPOUT VH VH
VOS
COMP0
Figure 41. Comparator Hysteresis Transfer Function
Hysteresis
Figure 41 shows how the input offset voltage and hysteresis terms are defined. Input offset voltage (VBOSB) is the difference between the center of the hysteresis range and the ground level. This can either be positive or negative. The hysteresis voltage (VBH) is one-half the width of the hysteresis range.
B
ADC2/CMP0 MUX ADC3/CMP1 MUX REF P0.0/CMP OUT
PLA IRQ ADC START CONVERSION
Figure 42: Comparator
The comparator interface consists on a 16-bit MMR, CMPCON described below. Table 28: CMPCON MMR bit descriptions Bit 15-11 10 CMPEN Name Description Reserved Comparator enable bit: Set by user to enable the comparator, Note: A comparator interrupt will be generated on the enable of the comparator, this should be cleared in the user software. Cleared by user to disable the comparator Comparator negative input select bits: 00 AVDD/2 01 ADC3 input 10 Vref * 0.6 11 Reserved Comparator output configuration bits: 00 IRQ and PLA connections disabled 01 IRQ and PLA connections disabled 10 PLA Connections enabled 11 IRQ Connections enabled Comparator output logic state bit When low the comparator output is high when the positive input (CMP0) is above the negative input (CMP1). When high, the comparator output is high when the positive input is below the negative input Response time 5 s response time typical for large signals (2.5 V differential). 00
17 s response time typical for small signals (0.65 mV differential).
9-8
CMPIN
7-6
CMPOC
5
CMPOL
4-3
CMPRES
01 10 11
Reserved Reserved
3 s response time typical for any signal type.
Rev. PrA | Page 46 of 92
04955-063
Preliminary Technical Data
2 CMPHYST Comparator hysteresis bit: Set by user to have an hysteresis of about 7.5mV Cleared by user to have no hysteresis Comparator output rising edge interrupt Set automatically when a rising edge occurs on the monitored voltage (CMP0) Cleared by user by writing a 1 to this bit. Comparator output falling edge interrupt Set automatically when a falling edge occurs on the monitored voltage (CMP0) Cleared by user
ADUC7128
1
CMPORI
0
CMPOFI
Rev. PrA | Page 47 of 92
ADUC7128
Preliminary Technical Data
OSCILLATOR AND PLL - POWER CONTROL
The ADUC7128 integrates a 32.768kHz oscillator, a clock divider and a PLL. The PLL locks onto a multiple (1275) of the internal oscillator to provide a stable 41.78 MHz clock for the system. The core can operate at this frequency, or at binary submultiples of it, to allow power saving. The default core clock is the PLL clock divided by 8 (CD = 3) or 5.2 MHz. The core clock frequency can be outputted on the ECLK pin as described in the GPIO section. A power down mode is available on the ADUC7128. The operating mode, clocking mode and programmable clock divider are controlled via two MMRs, PLLCON and POWCON. PLLCON controls operating mode of the clock system while POWCON controls the core clock frequency and the powerdown mode.
WATCHDOG TIMER WAKEUP TIMER AT POWER UP OCLK 32.768kHz PLL 41.78MHz MDCLK I2C CD CORE * 32.768kHz +/-3% UCLK /2 CD HCLK ANALOG PERIPHERALS P0.7/XCLK INT. 32kHz * OSCILLATOR CRYSTAL OSCILLATOR XCLKO XCLKI
Figure 43: clocking system
External Crystal Selection
To switch to external crystal, clear the OSEL bit in the PLLCON MMR (see Table 31). In noisy environments, noise might couple to the external crystal pins and PLL could loose lock momentary. A PLL interrupt is provided in the interrupt controller. The core clock is halted immediately and this interrupt is only serviced once the lock has been restored. In case of crystal loss, the watchdog timer should be used. During initialisation a test on the RSTSTA can determine if the reset came from the watchdog timer.
External Clock Selection
To switch to an external clock on P0.7, configure P0.7 in Mode 1 and MDCLK bits to 11. External clock can be up to 44 MHz providing the tolerance is 1%.
P0.7/ECLK
Rev. PrA | Page 48 of 92
Preliminary Technical Data
Power Control System
ADUC7128
A choice of operating modes is available on the ADUC7128. Table 29 describes what part of the ADUC7128 is powered on in the different modes and indicates the power-up time. Table 30 gives some typical values of total the current consumption (analog + digital supply currents) in the different modes depending on the clock divider bits. The ADC is turned off. Note that these values also include current consumption of the regulator and other parts on the test board on which these values were measured. Table 29. Operating Modes
Mode Active Pause Nap Sleep Stop Core X Peripherals X X PLL X X X XTAL/T2/T3 X X X X XIRQ X X X X X Start up /power on Time TBD at CD = 0 TBD at CD = 0. 3.06 s at CD = 7 TBD at CD = 0. 3.06 s at CD = 7 TBD TBD
Table 30. Typical Current Consumption at 25C
PC[2-0] 000 001 010 011 100 Mode Active Pause Nap Sleep Stop CD = 0 CD = 1 CD = 2 CD = 3 CD = 4 CD = 5 CD = 6 CD = 7
MMRs and Keys
The operating mode, clocking mode and programmable clock divider are controlled via two MMRs, PLLCON (see Table 31) and POWCON (see Table 32). PLLCON controls operating mode of the clock system, while POWCON controls the core clock frequency and the power-down mode. To prevent accidental programming, a certain sequence, shown in Table 33, has to be followed to write in the PLLCON and POWCON registers.
POWCON Register
Name POWCON Address 0xFFFF0408 Default Value 0x0003 Access RW
Table 31. PLLCON MMR Bit Designations
Bit 7, 6 5 Value Name OSEL Description Reserved. 32k Hz PLL input selection. Set by the user to use the internal 32 kHz oscillator. Set by default. Cleared by user to use the external 32 kHz crystal. Reserved. Clocking modes. Reserved. PLL. Default configuration. Reserved. External clock on P0.7 pin.
PLLKEYx Register
Name PLLKEY1 PLLKEY2 Address 0xFFFF0410 0xFFFF0418 Default Value 0x0000 0x0000 Access W W
4, 3, 2 1, 0 00 01 10 11
MDCLK
PLLCON Register
Name PLLCON Address 0xFFFF0414 Default Value 0x21 Access RW
POWKEYx Register
Name POWKEY1 POWKEY2 Address 0xFFFF0404 0xFFFF040C Default Value 0x0000 0x0000 Access W W
Rev. PrA | Page 49 of 92
ADUC7128
Table 32. POWCON MMR Bit Designations
Bit 7 6. 5. 4 Value Name PC 000 001 010 011 Description Reserved. Operating modes. Active mode. Pause mode. Nap. Sleep mode. XIRQ0, XIRQ1, Timer2, and Timer3 can wake-up the ADUC7128 Stop mode. Reserved. Reserved CPU clock divider bits. 41.779200 MHz 20.889600 MHz 10.444800 MHz 5.222400 MHz 2.611200 MHz 1.305600 MHz 654.800 kHz 326.400 kHz
Preliminary Technical Data
100 Others 3 2, 1, 0 000 001 010 011 100 101 110 111 RSVD CD
Table 33. PLLCON and POWCON Write Sequence
PLLCON PLLKEY1 = 0xAA PLLCON = 0x01 PLLKEY2 = 0x55 POWCON POWKEY1 = 0x01 POWCON = User Value POWKEY2 = 0xF4
Rev. PrA | Page 50 of 92
Preliminary Technical Data
DIGITAL PERIPHERALS
PWM
General overview
The ADUC7128 integrates a six channel PWM interface. The PWM outputs can be configured to drive a H-Bridge or can be used as standard PWM outputs. On power up the PWM outputs default to H-Bridge mode. This ensures that the motor is turned off by default. In standard PWM mode the outputs are arranged as 3 pairs of PWM pins. Users have control over the period of each pair of outputs and of the duty cycle of each individual output.
ADUC7128
The PWM has the following MMRs Name PWMCON1 PWM1COM1 PWM1COM2 PWM1COM3 PWM1LEN PWM2COM1 PWM2COM2 PWM2COM3 PWM2LEN PWM3COM1 PWM3COM2 PWM3COM3 PWM3LEN PWMCON2 PWMICLR Function PWM Control Compare register 1 for PWM o/ps 1 and 2 Compare register 2 for PWM o/ps 1 and 2 Compare register 3 for PWM o/ps 1 and 2 Frequency Control for PWM o/ps 1 and 2 Compare register 1 for PWM o/ps 3 and 4 Compare register 2 for PWM o/ps 3 and 4 Compare register 3 for PWM o/ps 3 and 4 Frequency Control for PWM o/ps 3 and 4 Compare register 1 for PWM o/ps 5 and 6 Compare register 2 for PWM o/ps 5 and 6 Compare register 3 for PWM o/ps 5 and 6 Frequency Control for PWM o/ps 5 and 6 PWM Convert Start Control PWM Interrupt Clear
The PWM clock is selectable via PWMCON1 with one of the following values, UCLK /2, 4, 8, 16, 32, 64, 128 or 256. The length of a PWM period is defined by PWMxLEN. The PWM waveforms are set by the count value of the 16-bit timer and the compare registers contents as shown with the PWM1 and PWM2 waveforms above. The low-side waveform, PWM2, goes high when the timer count reaches PWM1LEN, and it goes low when the timer count reaches the value held in PWM1COM3 or when the high-side waveform PWM1 goes low. The high-side waveform, PWM1, goes high when the timer count reaches the value held in PWM1COM1, and it goes low when the timer count reaches the value held in PWM1COM2. Table 34. PWMCON1 MMR Bit Designations
Bit 14 Value Name SYNC Description Enables PWM synchronization Set to `1' by the user so that all PWM counters are reset on the next clock edge after the detection of a high to low transition on the SYNC pin. Cleared by the user to ignore transitions on the SYNC pin. Set to `1' by the user to invert PWM6 Cleared by the user to use PWM6 in normal mode. Set to `1' by the user to invert PWM4 Cleared by the user to use PWM4 in normal mode. Set to `1' by the user to invert PWM2 Cleared by the user to use PWM2 in normal mode. Set to `1' by the user to enable PWM trip interrupt. When the PWMTRIP input is low the PWMEN bit is cleared and an interrupt is generated.
In all modes the PWMxCOMx MMRs controls the point at which the PWM outputs change state. An example of the first pair of PWM outputs ( PWM1 and PWM2) is shown below. Figure 44 PWM Timing.
13
PWM6INV
12
PWM4NV
11
PWM2INV
10
PWMTRIP
Rev. PrA | Page 51 of 92
ADUC7128
9 ENA Cleared by the user to diable the PWMTRIP interrupt. If HOFF = 0 and HMODE = 1 Set to `1' by the user to enable PWM outputs Cleared by the user to disable PWM outputs. If HOFF=1 and HMODE=1, see table 51 In not H-Bridge mode this bit has no effect. PWM Clock prescaler bits. Sets UCLCK divider. 2 4 8 16 32 64 128 256 Set to `1' by the user to invert all PWM outputs Cleared by the user to use PWM outputs as normal. High side off. Set to `1' by the user to force PWM1 and PWM3 outputs high, this also forces PWM2 and PWM4 low. Cleared by the user to use the PWM outputs as normal Load compare regiseters. Set to `1' by the user to load the internal compare registers with the values in PWMxCOMx on the next transition of the PWM timer from 0x00 to 0x01. Cleared by the user to use the values previously stored in the internal compare registers. Direction Control Set to `1' by the user to enalble PWM1 and PWM2 as the output signals while PWM3 and PWM4 are held low. Cleared by the user to enable PWM3 and PWM4 as the output signals while PWM 1 and PWM2 are held low. Enables H-Bridge mode Set to `1' by the user to enable HBridge mode and bits 1-5 of PWMCON1. Cleared by the user to operate the PWMs in standard mode. Set to `1' by the user to enable all PWM outputs.
Preliminary Technical Data
In H-Bridge mdoe i.e. HMODE = 1 then the table below determines the PWM outputs. HS= High side, LS= Low side Table 35. PWMCOM1 MMR ENA 0 x 1 1 1 1 HOFF 0 1 0 0 0 0 POINV x x 0 0 1 1 DIR x x 0 1 0 1 PWM Outputs
PWM1 PWM2 PWMR3 PWM4
8 7 6 000 001 010 011 100 101 110 111 5
PWMCP2 PWMCP1 PWMCP0
1 1 0 HS !HS 1
1 0 0 LS !LS 1
1 1 HS 0 1 !HS
1 0 LS 0 1 !LS
POINV
4
HOFF
Note on POWERUP PWMCON1 defaults to 0x12 i.e. HOFF = 1 and HMODE = 1. All GPIO pins associated with the PWM are configured in PWM mode by default. The compare registers are detailed below.
3
LCOMP
2
DIR
Name PWM1COM1 PWM1COM2 PWM1COM3 PWM2COM1 PWM2COM2 PWM2COM3 PWM3COM1 PWM3COM2 PWM3COM3
Address 0xFFFF0F84 0xFFFF0F88 0xFFFF0F8C 0xFFFF0F94 0xFFFF0F98 0xFFFF0F9C 0xFFFF0FA4 0xFFFF0FA8 0xFFFF0FAC
Default Value 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
Access RW RW RW RW RW RW RW RW RW
The PWM Trip interrupt can be cleared by writing to the PWMICLR MMR. Note: When using the PWM trip interrupt users should make sure that the PWM interrupt has been cleared before exiting the ISR. This avoids multiple interrupts being generated. PWM Convert Start Control The PWM can be configured to generated an ADC convert start signal after the active low side signal goes high. There is a programmable delay between when the low side signal goes high and the Convert Start signal is generated. This is controlled via the PWMCON2 MMR. If the delay
1
HMODE
0
PWMEN
Rev. PrA | Page 52 of 92
Preliminary Technical Data
selected is higher than the width of the PWM pulse, the interrupt will remain low. Table 36. PWMCON2 MMR Bit Designations
Bit 7 Value Name CSEN Description Set to `1' by the user to enable the PWM to generate a convert start signal. Cleared by the user to diable the PWM convert start signal. Convert Start Delays. Delay the convert start signal by a number of clock pulses.
ADUC7128
30
CSD3 CSD2 CSD1 CSD0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64
When calculating the time from the convert start delay to the start of an ADC conversion the user needs to take account of internal delays. The example below shows the case for a delay of 4 clocks. One additional clock is required to pass the convert start signal to the ADC logic. Once the ADC logic receives the convert start signal an ADC conversion will begin on the next ADC clock edge. See figure 32 in the ADC section.
Uclock
Low Side
Count
PWM Signal to Convst
Signal Passed to ADC Logic
Rev. PrA | Page 53 of 92
ADUC7128
Quadrature Encoder A quadrature encoder is used to determine both the speed and direction of a rotating shaft. In it's most common form there are two digital outputs S1 and S2. As the shaft rotates both S1 and S2 will toggle, however they will be 90 out of phase. The leading output determines the direction of rotation. The time between each transition indicates the speed of rotation. Input Filtering
Preliminary Technical Data
Filtering can be applied to the S1 input by setting the FILTEN bit in QENCON. S1 normally acts as the clock to the counter, however the filter can be used to ignore positive edges on S1 unless there has been a high or a low pulse on S2 between two positive edges on S1. (See figure ).
Figure 46. S1 Input Filtering Table 37. QENCON MMR Bit Designations
Bit 1511 10 Value Name Description Reserved. Set to `1' by the user to enable filtering on the S1 pin Cleared by the user do disable filtering on the S1 pin. Reserved, This bit should be set to `0' by the user. Set to `1' by the user to invert the S2 intput. Cleared by the user to use the S2 input as normal. If the DIRCON bit is set, then S2INV controls the direction fo the counter. In this case: Set to `1' by the user to operate the counter in increment mode. Cleared by the user to operate the counter in decrement mode. Set to `1' by the user to invert the S1 intput. Cleared by the user to use the S1 input as normal. Direction Control. Set to `1' by the user to enable S1 as the input to the counter clock. The driection of the counter is controlled via the S2INV bit. Cleared by the user to operated in normal mode. Set to `1' by the user to geneate an IRQ when a low to high transition is
Figure 45. Quadrate Encoder Input Values The quadrature encoder takes the incremental input shown above and increments or decrements a counter depending on the direction and speed of the rotating shaft. On the ADUC7128, the internal counter is clocked on the rising edge of the S1 input, the S2 input indicates the direction of rotation/count. The counter increments when S2 is high and decrements when it is low. In addition, if the software has prior knowledge of the direction of rotation. Then one input can be ignored (S2) and the other can act as a clock (S1). For added flexibility, all inputs can be internally inverted prior to use. The Quadrature Encoder operates asynchronously from the system clock.
FILTEN
9 8
RSVD S2INV
7
S1INV
6
DIRCON
5
S1IRQEN
Rev. PrA | Page 54 of 92
Preliminary Technical Data
detected on S1. Cleared by the user to disable the interrupt. This bit should be set to `0' by the user. Underflow IRQ enable. Set to `1' by the user to generate an interrupt if QENVAL underflows. Cleared by the user to disable the interrupt. Overflow IRQ enable. Set to `1' by the user to generate an interrupt if QENVAL overflows. Cleared by the user to disable the interrupt. This bit should be set to `0' by the user. Enable Quadrature Encoder Set to `1' by the user to enable the quadrature encoder. Cleared by the user to diable the quadrature encoder.
ADUC7128
QENDAT. Table 40. QENVAL
Name QENVAL Address 0xFFFF0F0C Default Value 0x0000 Access RW
4 3
RSVD UIRQEN
This register contains the current value of the Quadrature Encoder counter. Table 41. QENCLR
Name QENCLR Address 0xFFFF0F14 Default Value 0x00000000 Access RW
2
OIREQEN
Writing any value to this register clears the QENVAL register to 0x0000. The bits in this register are undefined. Table 42. QENSET
Name QENSET Address 0xFFFF0F18 Default Value 0x00000000 Access RW
1 0
RSVD ENQEN
Writing any value to this register loads the QENVAL register with the value in QENDAT. The bits in this register are undefined. Note:
Table 38. QENSTA MMR Bit Designations
Bit 7-5 4 Value Name S1EDGE Description Reserved. S1 rising edge. This bit is set automatically on a rising edge of S1 Cleared by reading QENSTA Reserved. Underflow flag This bit is set automatically if an underflow occurs. Cleared by read QENSTA This bit is set automatically if an overflow has occurred. Cleared by reading QENSTA Direction of the counter Set to `1' by hardare to idicate that the counter Is incrementing. Set to `0' by hardware to indicate that the counter is decrementing.
The interrupt conditions are ORed together to form one interrupt to the interrupt controller. The Interrupt Service Routine should check the QENSTA register to find out the cause of the interrupt. * * * The S1 and S2 inputs shall appear as the QENS1 and QENS2 inputs in the GPIO list. The motor speed can be measured by using the capture facility in Timer 0 or Timer 1. An overflow of either timer can be checked by using an ISR or by checking IRQSIG. The counter with the quadrature encoder is gray encoded to ensure reliable data transfer across clock boundaries. When an underflow or overflow occurs the count value does not jump to the other end of the scale, instead the direction of count changes. When this happens the value in QENDAT is subtracted from the value derived from the gray count. When the value in QENDAT changes the value read back from QENVAL changes, however the gray encoded value will not change. This will only occur after an underflow or overflow. If the value in QENDAT changes then there must be a write to QENSET or QENCLR to ensure that a valid number is read back from QENVAL.
3 2
RSVD UNDER
1
OVER
0
DIR
Table 39. QENDAT
Name QENDAT Address 0xFFFF0F08 Default Value 0Xffff Access RW
This register holds the maximum value allowed for the QENVAL register. If the QENVAL register increments past the value in this register then an overflow condition occurs. When an overflow occurs the QENVAL register is reset to 0x0000. When the QENVAL register decrements past zero during an underflow it will be loaded with the value in
Rev. PrA | Page 55 of 92
ADUC7128
GENERAL PURPOSE I/O
The ADUC7128 provides 28 general purpose, bi-directional I/O (GPIO) pind. All I/O pins are 5 V tolerant, which means that the GPIOs support an input voltage of 5 V. In general, many of the GPIO pins have multiple functions (see the pin function definitions on page 14). By default, the GPIO pins are configured in GPIO mode. All GPIO pins have internal pull-up resistor (of about 100 k) and their drive capability is 1.6 mA. Note that a maximum of 20 GPIO can drive 1.6 mA at the same time. The following GPIO have programmable pull up: P0.0, P0.4, P0.5, P0.6, P0.7, and the 8 GPIOs of P1. The 40 GPIO are grouped in 5 ports, Port 0 to Port 4. Each port is controlled by four or five MMRs, x representing the port number.
3 2 P1.7 P2.0 P2.12 P2.22 P2.32 P2.42 P2.52 P2.62 P2.72 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.62 P3.72 P4.0 P4.1 P4.2 P4.3
Preliminary Technical Data
GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO DTR0 SYNC RTS1 CTS1 RI1 DCD1 DSR1 DTR1 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM1 PWM3 QENS1 QENS2 RSVD Trip (Shutdown) P4.4 P4.5 P4.6 P4.7
1
P PWhen
4
GPxCON Register
Name GP0CON GP1CON GP2CON GP3CON GP4CON Address 0xFFFF0D00 0xFFFF0D04 0xFFFF0D08 0xFFFF0D0C 0xFFFF0D10 Default Value 0x00000000 0x00000000 0x00000000 Access RW RW RW RW RW
CSL SOUT WS RS AE MS0 MS1 MS2 MS3 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11
PLAO[0] PLAO[5] PLAO[6] PLAO[7]
PLAI[8] PLAI[9] PLAI[10] PLAI[11] PLAI[12] PLAI[13] PLAI[14] PLAI[15] PLAO[8] PLAO[9] PLAO[10] PLAO[11]
GPIO GPIO GPIO GPIO
0x11111111
0x00000000
PLMIN PLMOUT SIN1 SOUT1
AD12 AD13 AD14 AD15
PLAO[12] PLAO[13] PLAO[14] PLAO[15]
Note that the kernel changes P0.6 from its default configuration at reset (MRST) to GPIO mode. If MRST is used for external circuitry, an external pull-up resistor should be used to insure that the level on P0.6 does not drop when the kernel switches mode. For example, if MRST is required for power down, it can be reconfigured in GP0CON MMR. GPxCON is the port x control register, and selects the function of each pin of port X. as described in Table 43. Table 43. GPIO Pin Function Descriptions
Port 0 Pin P0.0 P0.12 P0.22 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 00 GPIO GPIO GPIO GPIO GPIO/IRQ0 GPIO/IRQ1 GPIO/T1 GPIO GPIO/T1 GPIO GPIO GPIO GPIO/IRQ2 GPIO/IRQ3 GPIO Configuration 01 10 CMP MS2 BLE BHE TRST A16 MS1 CONVSTART ADCBBUSYB PLM_COMP MRST AE ECLK/XCLKP1 SIN0 SIN0 SCL0 SOUT0 SDA0 RTS0 SCL1 CTS0 SDA1 RI0 CLK DCD0 MISO DSR0 MOSI
E A EA P
configured in Mode 1, PO.7 is ECLK by default, or core clock output. To configure it as a clock output, MDCLK bits in PLLCON must be set to 11. Only available on 80 pin ADuC7129 part.
2
Table 44. GPxCON MMR Bit Descriptions
Bit 31, 30 29, 28 27, 26 25, 24 23, 22 21, 20 19, 18 17, 16 15, 14 13, 12 11, 10 9, 8 7, 6 5, 4 3, 2 1, 0 Description Reserved Select function of Px.7 Pin Reserved Select function of Px.6 Pin Reserved Select function of Px.5 Pin Reserved Select function of Px.4 Pin Reserved Select function of Px.3 Pin Reserved Select function of Px.2 Pin Reserved Select function of Px.1 Pin Reserved Select function of Px.0 Pin
11 PLAI[7] ADCBBUSYB PLAO[1] PLAO[2] PLAO[3] PLAO[4] PLAI[0] PLAI[1] PLAI[2] PLAI[3] PLAI[4] PLAI[5] PLAI[6]
1
Rev. PrA | Page 56 of 92
Preliminary Technical Data
GPxPAR Register
Name GP0PAR GP1PAR GP3PAR GP4PAR Address 0xFFFF0D2C 0xFFFF0D3C 0xFFFF0D5C 0xFFFF0D6C Default Value 0x20000000 0x00000000 0x00222222 0x00000000 Access RW RW RW RW 15 to 8 7 to 0
ADUC7128
Reflect the state of port x pins at reset (read only). Port x data input (read only).
GPxSET Register
Name GP0SET GP1SET GP2SET GP3SET GP4SET Address 0xFFFF0D24 0xFFFF0D34 0xFFFF0D44 0xFFFF0D54 0xFFFF0D64 Default Value 0x000000XX 0x000000XX 0x000000XX 0x000000XX 0x000000XX Access W W W W W
GPxPAR programs the parameters for Port 0, Port 1,,Port 3 and Port 4. Note that the GPxDAT MMR must always be written after changing the GPxPAR MMR. Table 45. GPxPAR MMR Bit Descriptions
Bit 31 to 29 28 27, 26, 25 24 23, 22, 21 20 19 , 18, 17 16 15, 14, 13 12 11, 10, 9 8 7, 6, 5 4 3, 2, 1 0 Description Reserved Pull up disable Px.7 Reserved Pull up disable Px.6 Reserved Pull up disable Px.5 Reserved Pull up disable Px.4 Reserved Pull up disable Px.3 Reserved Pull up disable Px.2 Reserved Pull up disable Px.1 Reserved Pull up disable Px.0
GPxSET is a data set port x register. Table 47. GPxSET MMR Bit Descriptions
Bit 31 to 24 23 to 16 Description Reserved. Data port x set bit. Set to 1 by the user to set bit on port x; also sets the corresponding bit in the GPxDAT MMR. Clear to 0 by the user; does not affect the data out. Reserved.
15 to 0
GPxCLR Register
Name GP0CLR GP1CLR GP2CLR GP3CLR GP4CLR Address 0xFFFF0D28 0xFFFF0D38 0xFFFF0D48 0xFFFF0D58 0xFFFF0D68 Default Value 0x000000XX 0x000000XX 0x000000XX 0x000000XX 0x000000XX Access W W W W W
GPxCLR is a data clear port x register.
GPxDAT Register
Name GP0DAT GP1DAT GP2DAT GP3DAT GP4DAT Address 0xFFFF0D20 0xFFFF0D30 0xFFFF0D40 0xFFFF0D50 0xFFFF0D60 Default Value 0x000000XX 0x000000XX 0x000000XX 0x000000XX 0x000000XX Access RW RW RW RW RW
Table 48. GPxCLR MMR Bit Descriptions
Bit 31 to 24 23 to 16 Description Reserved. Data port x clear bit. Set to 1 by the user to clear bit on port x; also clears the corresponding bit in the GPxDAT MMR. Clear to 0 by the user does not affect the data out. Reserved.
GPxDAT is a port x configuration and data register. It configures the direction of the GPIO pins of port x, sets the output value for the pins configured as output, and receives the stores the input value of the pins configured as input. Table 46. GPxDAT MMR Bit Descriptions
Bit 31 to 24 Description Direction of the data. Set to 1 by the user to configure the GPIO pin as an output. Clear to 0 by the user to configure the GPIO pin as an input. Port x data output.
15 to 0
23 to 16
Rev. PrA | Page 57 of 92
ADUC7128
SERIAL PORT MUX
The Serial Port Mux multiplexes the serial port peripherals (two I2C, SPI, two UARTs) and the Programmable Logic Array (PLA) to a set of ten GPIO pins. Each pin must be configured to one of its specific I/O function as described in Table 49. GPIO 00 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P0.7 P2.01 P2.21 P2.31 P2.41 P2.51 P2.61 P2.71 P4.6 P4.7 UART 01 SIN0 SOUT0 RTS0 CTS0 RI0 DCD0 DSR0 DTR0 ECLK PWMSYNC RTS1 CTS1 RI1 DCD1 DSR1 DTR1 SIN1 SOUT1 UART/IP2 10 I2C0SCL I2C0SDA I2C1SCL I2C1SDA SPICLK SPIMISO SPIMOSI SPICSL SIN0 SOUT0 RS AE MS0 MS1 MS2 MS3
AD14 AD15
PC/SPI
Preliminary Technical Data
SPM0 SPM1 SPM2 SPM3 SPM4 SPM5 SPM6 SPM7 SPM8 SPM9
SPM10 SPM11 SPM12 SPM13 SPM14 SPM15 SPM16 SPM17
PLA 11 PLAI[0] PLAI[1] PLAI[2] PLAI[3] PLAI[4] PLAI[5] PLAI[6] PLAO[0] PLAO[4] PLAO[5] PLAO[7]
Pin SPM0 (mode 1) SPM1 (mode 1) SPM2 (mode 1) SPM3 (mode 1) SPM4 (mode 1) SPM5 (mode 1) SPM6 (mode 1) SPM7 (mode 1) SPM8 (mode 2) SPM9 (mode 2)
Signal SIN0 SOUT0 RTS0 CTS0 RI0 DCD0 DSR0 DTR0 SIN0 SOUT0
Description Serial Receive Data Serial Transmit Data Request To Send Clear To Send Ring Indicator Data Carrier Detect Data Set Ready Data Terminal Ready Serial Receive Data Serial Transmit Data
Table 50: UART signal description
The serial communication adopts a asynchronous protocol that supports various word length, stop bits and parity generation options selectable in the configuration register.
Baud rate generation
There is two way of generating the UART baudrate. - Normal 450 UART baudrate generation: The baudrate is a divided version of the core clock using the value in COM0DIV0 and COM0DIV1 MMRs (16-bit value, DL).
Baud rate = 41.78 MHz 2 x 16 x 2 x DL
CD
PLAO[14] PLAO[15]
Table 49: SPM configuration
1
Only available on 80 pin part.
The following table gives some common baudrate values:
Baud Rate 9600 19200 115200 9600 19200 115200 CD 0 0 0 3 3 3 DL 88 h 44 h 0B h 11 h 8h 1h Actual Baud Rate 9600 19200 118691 9600 20400 163200 % Error 0% 0% 3% 0% 6.25% 41.67%
Table 49 details the mode for each of the SPMUX GPIO pins. This configuration has to be done via the GP0CON, GP1CON and GP2CON MMRs. By default these 17 pins are configured as GPIOs.
UART SERIAL INTERFACE
The ADUC7128 contains two identical UART blocks. Only UART0 is described here, UART1 functions in the exact same manner. The UART peripheral is a full-duplex Universal Asynchronous Receiver/Transmitter, fully compatible with the 16450 serial port standard. The UART performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters received from the CPU. The UART includes a fractional divider for baudrate generation and has a network addressable mode. The UART function is made available on the following 10 pins of the ADUC7128:
Table 51: baudrate using the normal baudrate generator
- Using the fractional divider: The fractional divider combined with the normal baudrate generator allows the generating of a wider range of more accurate baudrates.
Rev. PrA | Page 58 of 92
Preliminary Technical Data
Core Clock /2 FBEN
ADUC7128
UART registers definition
The UART interface consists on 12 registers namely:
/16DL /(M+N/2048)
UART
Figure 47: baudrate generation options
Calculation of the baudrate using fractional divider is as follow:
Baud rate =
41.78 MHz 2 CD x16 x DL x 2 x ( M + N ) 2048
M+
41.78 MHz N = 2048 Baud rate x 2 CD x16 x DL x 2
For example: Generation of 19200 baud with CD bits = 3 (Table 51 gives DL = 8 h).
M+ 41.78 MHz N = 2048 19200 x 2 3 x 16 x 8 x 2
- COMxTX: 8-bit transmit register - COMxRX: 8-bit receive register - COMxDIV0: divisor latch (low byte) COMTX, COMRX and COMDIV0 share the same address location. COMTX and COMTX can be accessed when bit 7 in COMCON0 register is cleared. COMDIV0 can be accessed when bit 7 of COMCON0 is set. - COMxDIV1: divisor latch (high byte) - COMxCON0: line control register - COMxSTA0: line status register - COMxIEN0: interrupt enable register - COMxIID0: interrupt identification register - COMxCON1: modem control register - COMxSTA1: modem status register - COMxDIV2: 16-bit fractional baud divide register - COMxSCR: 8-bit scratch register used for temporary storage. Also used in network addressable UART mode.
M+
N = 1.06 2048
where: M=1 N = 0.06 x 2048 = 128
Baud rate = 41.78 MHz 128 2 3 x 16 x 8 x 2 x 2048
(
)
where: Baud rate = 19200 bps Error = 0% compared to 6.25% with the normal baud rate generator.
Table 52: COMxCON0 MMR Bit Descriptions Bit 7 Name DLAB Description Divisor latch access Set by user to enable access to COMDIV0 and COMDIV1 registers Cleared by user to disable access to COMDIV0 and COMDIV1 and enable access to COMRX and COMTX Set break. Set by user to force SOUT to 0 Cleared to operate in normal mode Stick parity Set by user to force parity to defined values: 1 if EPS = 1 and PEN = 1 0 if EPS = 0 and PEN = 1 Even parity select bit Set for even parity Cleared for odd parity
6 5
BRK SP
4
EPS
Rev. PrA | Page 59 of 92
ADUC7128
3 2 PEN STOP
Preliminary Technical Data
Parity enable bit: Set by user to transmit and check the parity bit Cleared by user for no parity transmission or checking Stop bit Set by user to transmit 1.5 Stop bit if the Word Length is 5 bits or 2 Stop bits if the word length is 6, 7 or 8 bits. The receiver checks the first Stop bit only, regardless of the number of Stop bits selected Cleared by user to generate 1 Stop bit in the transmitted data Word length select: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits
1-0
WLS
Rev. PrA | Page 60 of 92
Preliminary Technical Data
Table 53: COMxSTA0 MMR Bit Descriptions Bit 7 6 5 4 3 2 1 0 TEMT THRE BI FE PE OE DR Name Description Reserved COMTX empty status bit Set automatically if COMTX is empty Cleared automatically when writing to COMTX COMTX and COMRX empty Set automatically if COMTX and COMRX are empty Cleared automatically when one of the register receives data Break error Set when SIN is held low for more than the maximum word length Cleared automatically Framing error Set when invalid stop bit Cleared automatically Parity error Set when a parity error occurs Cleared automatically Overrun error Set automatically if data are overwrite before been read Cleared automatically Data ready Set automatically when COMRX is full Cleared by reading COMRX
ADUC7128
Table 54: COMxIEN0 MMR Bit Descriptions Bit 7-4 3 2 1 0 EDSSI ELSI ETBEI ERBFI Name Description Reserved Modem status interrupt enable bit Set by user to enable generation of an interrupt if any of COMSTA1[3:0] are set Cleared by user RX status interrupt enable bit Set by user to enable generation of an interrupt if any of COMSTA0[3:0] are set Cleared by user Enable transmit buffer empty interrupt Set by user to enable interrupt when buffer is empty during a transmission Cleared by user Enable receive buffer full interrupt Set by user to enable interrupt when buffer is full during a reception Cleared by user
Table 55: COMxIID0 MMR Bit Descriptions Bit 2-1 Status bits 00 11 10 01 00 Bit 0 NINT 1 0 0 0 0 1 2 3 4 No interrupt Receive line status interrupt Receive buffer full interrupt Transmit buffer empty interrupt Modem status interrupt Read COMSTA0 Read COMRX Write data to COMTX or read COMIID0 Read COMSTA1 register Priority Definition Clearing operation
Rev. PrA | Page 61 of 92
ADUC7128
Bit 7-5 4 LOOPBACK Name Description Reserved
Preliminary Technical Data
Table 56: COMxCON1 MMR Bit Descriptions
1 0
RTS DTR
Loop back Set by user to enable loop back mode. In loop back mode the SOUT is forced high. Also the modem signals are directly connected to the status inputs (RTS to CTS, DTR to DSR, OUT1 to RI and OUT2 to DCD) Request to send Set by user to force the RTS output to 0 Cleared by user to force the RTS output to 1 Data terminal ready Set by user to force the DTR output to 0 Cleared by user to force the DTR output to 1
Table 57: COMxSTA1 MMR Bit Descriptions Bit 7 6 5 4 3 2 1 0 Name DCD RI DSR CTS DDCD TERI DDSR DCTS Description Data carrier detect Ring indicator Data set ready Clear to send Delta DCD Set automatically if DCD changed state since COMSTA1 last read Cleared automatically by reading COMSTA1 Trailing edge RI Set if NRI changed from 0 to 1 since COMSTA1 last read Cleared automatically by reading COMSTA1 Delta DSR Set automatically if DSR changed state since COMSTA1 last read Cleared automatically by reading COMSTA1 Delta CTS Set automatically if CTS changed state since COMSTA1 last read Cleared automatically by reading COMSTA1
Table 58: COMxDIV2 MMR Bit Descriptions Bit 15 14-13 12-11 10-0 FBM[1-0] FBN[10-0] Name FBEN Description Fractional baudrate generator enable bit Set by user to enable the fractional baudrate generator Cleared by user to generate baudrate using the standard 450 UART baudrate generator Reserved M. if FBM = 0, M = 4 N
Rev. PrA | Page 62 of 92
Preliminary Technical Data
Network addressable UART mode
This mode allows connecting the MicroConverter on a 256node serial network, either as a hardware single-master or via software in a multi-master network. Bit 7 of COMxIEN1 (ENAM bit) must be set to enable UART in network addressable mode. Note that there is no parity check in this mode, the parity bit is used for address.
ADUC7128
In network address mode, the least significant bit of the scratch register is the transmitted network address control bit. If set to 1, the device is transmitting an address. If cleared to 0, the device is transmitting data. - COMxIEN1: 8-bit network enable register. - COMxIID1: 8-bit network interrupt register. Bit 7 to 4 are reserved. See Table 54. - COMxADR: 8-bit read and write network address register. Holds the address the network addressable UART checks for. On receiving this address the device interrupts the processor and/or sets the appropriate status bit in COMIID1. COMIEN1, COMIID1 and COMADR are used only in network addressable UART mode.
Network addressable UART register definitions
Three additional register: - COMxSCR: 8-bit scratch register used for temporary storage.
Table 59: COMxIEN1 MMR Bit Descriptions Bit 7 6 5 4 3 2 1 0 Name ENAM E9BT E9BR ENI E9BD ETD NABP NAB Description Network address mode Enable bit set by user to enable network address mode cleared by user to disable network address mode 9-bit transmit enable bit Set by user to enable 9-bit transmit. ENAM must be set Cleared by user to disable 9-bit transmit 9-bit receive enable bit Set by user to enable 9-bit receive. ENAM must be set Cleared by user to disable 9-bit receive network interrupt Enable bit Word length Set for 9-bit data. E9BT has to be cleared. Cleared for 8-bit data Transmitter pin driver Enable bit Set by user to enable SOUT pin as an output in slave mode or multi-master mode Cleared by user, SOUT is three-state Network address bit, interrupt polarity bit Network address bit Set by user to transmit the slave's address Cleared by user to transmit data
Table 60: COMxIID1 MMR Bit Descriptions Bit 3-1 Status bits 000 110 101 011 010 001 000 Bit 0 NINT 1 0 0 0 0 0 0 2 3 1 2 3 4 No interrupt Matching network address Address transmitted, buffer empty Receive line status interrupt Receive buffer full interrupt Transmit buffer empty interrupt Modem status interrupt Read COMxRX Write data to COMTX or read COMxIID0 Read COMxSTA0 Read COMxRX Write data to COMxTX or read COMxIID0 Read COMxSTA1 register priority Definition Clearing operation
Rev. PrA | Page 63 of 92
ADUC7128
SERIAL PERIPHERAL INTERFACE
The ADUC7128 integrates a complete hardware serial peripheral interface (SPI) on-chip. SPI is an industry standard synchronous serial interface that allows eight bits of data to be synchronously transmitted and simultaneously received, that is, full duplex up to a maximum bit rate of 1.6 Mb. The SPI interface is only operational with core clock divider bits POWCON[2:0] = 0, 1, or 2. The SPI port can be configured for master or slave operation and typically consists of four pins, namely: MISO, MOSI, SCL, and CS.
Preliminary Technical Data
Chip Select (CS) Input Pin
In SPI slave mode, a transfer is initiated by the assertion of CS ,. which is an active low input signal. The SPI port then transmits and receives 8-bit data until the transfer is concluded by desassertion of CS . In slave mode, CS is always an input.
A E EA A E EA A E EA
SPI Registers
The following MMR registers are used to control the SPI interface: SPISTA, SPIRX, SPITX, SPIDIV, and SPICON.
SPISTA Register
Name SPISTA Address 0xFFFF0A00 Default Value 0x00 Access RW
MISO (Master In, Slave Out) Data I/O Pin
The MISO pin is configured as an input line in master mode and an output line in slave mode. The MISO line on the master (data in) should be connected to the MISO line in the slave device (data out). The data is transferred as byte wide (8-bit) serial data, MSB first.
SPISTA is an 8-bit read only status register. Table 61. SPISTA MMR Bit Descriptions
Bit 7, 6 5 4 3 Description Reserved. SPIRX data register overflow status bit. Set if SPIRX is overflowing. Cleared by reading SPISRX register. SPIRX data register IRQ. Set automatically if Bit 3 or Bit 5 is set. Cleared by reading SPIRX register. SPIRX data register full status bit. Set automatically if a valid data is present in the SPIRX register. Cleared by reading SPIRX register. SPITX data register underflow status bit. Set automatically if SPITX is under flowing. Cleared by writing in the SPITX register. SPITX data register IRQ. Set automatically if bit 0 is clear or bit 2 is set. Cleared by writing in the SPITX register or if finished transmission disabling the SPI. SPITX data register empty status bit. Set by writing to SPITX to send data. This bit is set during transmission of data. Cleared when SPITX is empty.
MOSI (Master Out, Slave In) Pin
The MOSI pin is configured as an output line in master mode and an input line in slave mode. The MOSI line on the master (data out) should be connected to the MOSI line in the slave device (data in). The data is transferred as byte wide (8-bit) serial data, MSB first.
2
1
SCL (Serial Clock) I/O Pin
The master serial clock (SCL) is used to synchronize the data being transmitted and received through the MOSI SCL period. Therefore, a byte is transmitted/received after eight SCL periods. The SCL pin is configured as an output in master mode and as an input in slave mode. In master mode, polarity and phase of the clock are controlled by the SPICON register, and the bit rate is defined in the SPIDIV register as follows:
0
SPIRX Register
Name SPIRX Address 0xFFFF0A04 Default Value 0x00 Access R
SPIRX is an 8-bit read only receive register.
f serialclock =
f HCLK 2 x (1 + SPIDIV )
SPITX Register
Name SPITX Address 0xFFFF0A08 Default Value 0x00 Access W
In slave mode, the SPICON register must be configured with the phase and polarity of the expected input clock. The slave accepts data from an external master up to 1.6 Mbs at CD = 0. In both master and slave modes, data is transmitted on one edge of the SCL signal and sampled on the other. Therefore, it is important that the polarity and phase are configured the same for the master and slave devices.
SPITX is an 8-bit write only transmit register.
SPIDIV Register
Name SPIDIV Address 0xFFFF0A0C Default Value 0x1B Access RW
SPIDIV is an 8-bit serial clock divider register.
Rev. PrA | Page 64 of 92
Preliminary Technical Data
SPICON Register
Name SPICON Address 0xFFFF0A10 Default Value 0x0000 Access RW
ADUC7128
SPICON is a 16-bit control register.
Table 62. SPICON MMR Bit Descriptions
Bit 15 - 13 12 Description Reserved. Continuous Transfer Enable. Set by user to enable continuous transfer. In master mode, the transfer continues until no valid data is available in the TX register. CS is asserted and remains asserted for the duration of each 8-bit serial transfer until TX is empty. Cleared by user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data exists in the SPITX register, then a new transfer is initiated after a stall period. Loop Back Enable. Set by user to connect MISO to MOSI and test software. Cleared by user to be in normal mode. Slave Output Enable. Set by user to enable the slave output. Cleared by user to disable slave output. Slave Select Input Enable. Set by user in master mode to enable the output. SPIRX Overflow Overwrite Enable. Set by user, the valid data in the RX register is overwritten by the new serial byte received. Cleared by user, the new serial byte received is discarded. SPITX Underflow Mode. Set by user to transmit 0. Cleared by user to transmit the previous data. Transfer and Interrupt Mode (Master Mode). Set by user to initiate transfer with a write to the SPITX register. Interrupt occurs when TX is empty. Cleared by user to initiate transfer with a read of the SPIRX register. Interrupt occurs when RX is full. LSB First Transfer Enable Bit. Set by user, the LSB is transmitted first. Cleared by user, the MSB is transmitted first. Reserved. Should be set to `0' Serial Clock Polarity Mode Bit. Set by user, the serial clock idles high. Cleared by user, the serial clock idles low. Serial Clock Phase Mode Bit. Set by user, the serial clock pulses at the beginning of each serial bit transfer. Cleared by user, the serial clock pulses at the end of each serial bit transfer. Master Mode Enable Bit. Set by user to enable master mode. Cleared by user to enable slave mode. SPI Enable Bit. Set by user to enable the SPI. Cleared to disable the SPI.
11 10 9 8 7 6 5 4 3 2 1 0
Rev. PrA | Page 65 of 92
ADUC7128
I2C COMPATIBLE INTERFACES
The ADUC7128 supports two fully licensed IP2 interfaces. The IP2 interfaces are both implemented as a full hardware master and slave interface. Because the two IP2 interfaces are identical, this document describes only I2C0 in detail. Note that the two masters and slaves have individual interrupts.
PC PC PC
Preliminary Technical Data
The I2CxDIV register corresponds to DIVH:DIVL.
Slave Addresses
The registers I2C0ID0, I2C0ID1, I2C0ID2 and I2C0ID3 contain the device IDs. The device compares the four I2C0IDx registers to the address byte. The seven most significant bits of either ID register must be identical to that of the seven most significant bits of the first address byte received to be correctly addressed. The LSB of the ID registers, transfer direction bit, is ignored in the process of address recognition.
The two pins used for data transfer, SDA and SCL, are configured in a Wired-AND format that allows arbitration in a multi-master system. The I2C bus peripheral's addresses in the I2C bus system is programmed by the user. This ID can be modified any time a transfer is not in progress. The user can configure the interface to respond to four slave addresses. The transfer sequence of an I2C system consists of a master device initiating a transfer by generating a start condition while the bus is idle. The master transmits the address of the slave device and the direction of the data transfer in the initial address transfer. If the master does not loose arbitration and the slave acknowledges, then the data transfer is initiated. This continues until the master issues a stop condition and the bus becomes idle. The I C peripheral master and slave functionality are independent and can be simultaneously active. A slave is activated when a transfer has been initiated on the bus. If it is not addressed, it remains inactive until another transfer is initiated. This also allows a master device, which looses arbitration, to respond as a slave in the same cycle.
2
IP2 Registers
PC
The I C peripheral interface consists of 18 MMRs, which are discussed in this section.
2
I2CxMSTA Register
Name I2C0MSTA I2C1MSTA Address 0xFFFF0800 0xFFFF0900 Default Value 0x00 0x00 Access R R
I2CxMSTA is a status register for the master channel. Table 63. I2C0MSTA MMR Bit Descriptions
Bit 7 6 Description Master busy. Set automatically if the master is busy. Cleared automatically. Arbitration loss. Set in multi-master mode if another master has the bus. Cleared when the bus becomes available. No ACK. Set automatically. If the master receive FIFO is full, the master does not acknowledge the data received. Cleared automatically. Master receive FIFO overflow. Set automatically if the master receive FIFO is overflowing. Cleared automatically by reading I2C0MRX. Master receive IRQ. Set after receiving data. Cleared automatically by reading the I2C0MRX register. Master transmit IRQ. Set at the end of a transmission. Cleared automatically by writing to the I2C0MTX register. Master transmit FIFO underflow. Set automatically if the master transmit FIFO is underflowing. Cleared automatically by writing to the I2C0MTX register. Master TX FIFO empty. Set automatically if the master transmit FIFO is empty. Cleared automatically by writing to the I2C0MTX register.
5
Serial Clock Generation
The I2C master in the system generates the serial clock for a transfer. The master channel can be configured to operate in fast mode (400 kHz) or standard mode (100 kHz). The bit rate is defined in the I2C0DIV MMR as follows:
4
3 2
f serialclock =
f UCLK (2 + DIVH ) + (2 + DIVL)
1
0
where: fBUCLKB = clock before the clock divider DIVH = the high period of the clock DIVL = the low period of the clock. Thus, for 100 kHz operation, DIVH = DIVL = 0xCF and for 400 kHz, DIVH = DIVL = 0x32.
Rev. PrA | Page 66 of 92
Preliminary Technical Data
I2CxSSTA Register
Name I2C0SSTA I2C1SSTA Address 0xFFFF0804 0xFFFF0904 Default Value 0x01 0x01 Access R R
ADUC7128
I2CxSSTA is a status register for the slave channel.
Table 64. I2CxSSTA MMR Bit Descriptions
Bit 31 to 15 14 Value Description Reserved. These bits should be written as 0. START decode bit. Set by hardware if the device receives a valid START + matching address. Cleared by an I2C stop condition or an I2C general call reset. Repeated START decode bit. Set by hardware if the device receives a valid repeated start + matching address. Cleared by an I2C stop condition, a read of the I2CSSTA register, or an I2C general call reset. ID decode bits. 00 01 10 11 10 Received address matched ID register 0. Received address matched ID register 1. Received address matched ID register 2. Received address matched ID register 3. Stop after start and matching address interrupt. Set by hardware if the slave device receives an I2C STOP condition after a previous I2C START condition and matching address. Cleared by a read of the I2CxSSTA register. General call ID. No general call. General call reset and program address. General call program address. General call matching alternative ID. General call interrupt. Slave Busy. Set automatically if the slave is busy. Cleared automatically. No ACK. Set if master asking for data and no data is available. Cleared automatically. Slave receive FIFO overflow. Set automatically if the slave receive FIFO is overflowing. Cleared automatically by reading I2C0SRX. Slave receive IRQ. Set after receiving data. Cleared automatically by reading the I2C0SRX register. Slave Transmit IRQ. Set at the end of a transmission. Cleared automatically by writing to the I2C0STX register. Slave transmit FIFO underflow. Set automatically if the slave transmit FIFO is underflowing. Cleared automatically by writing to the I2C0STX register. Slave transmit FIFO empty. Set automatically if the slave transmit FIFO is empty. Cleared automatically by writing to the I2C0STX register.
I2CxSRX Register
Name I2C0SRX I2C1SRX Address 0xFFFF0808 0xFFFF0908 Default Value 0x00 0x00 Access R R
I2CxSRX is a receive register for the slave channel.
13
I2CxSTX Register
Name I2C0STX I2C1STX Address 0xFFFF080C 0xFFFF090C Default Value 0x00 0x00 Access W W
12, 11
I2CxSTX is a transmit register for the slave channel.
I2CxMRX Register
Name I2C0MRX I2C1MRX Address 0xFFFF0810 0xFFFF0910 Default Value 0x00 0x00 Access R R
I2CxMRX is a receive register for the master channel.
I2CxMTX Register
Name I2C0MTX I2C1MTX Address 0xFFFF0814 0xFFFF0914 Default Value 0x00 0x00 Access W W
9, 8 00 01 10 11 7 6 5 4
I2CxSTX is a transmit register for the master channel.
I2CxCNT Register
Name I2C0CNT I2C1CNT Address 0xFFFF0818 0xFFFF0918 Default Value 0x00 0x00 Access RW RW
3 2
I2CxCNT is a master receive data count register. If a master read transfer sequence is initiated, the I2CxCNT register denotes the number of bytes (-1) to be read from the slave device. By default this counter is 0, which corresponds to expected 1 byte
I2CxADR Register
Name I2C0ADR I2C1ADR Address 0xFFFF081C 0xFFFF091C Default Value 0x00 0x00 Access RW RW
1
0
I2CxADR is a master address byte register. The I2CxADR value is the device address that the master wants to communicate with. It is automatically transmitted at the start of a master transfer sequence if there is no valid data in the I2CxMTX register when the master enable bit is set.
Rev. PrA | Page 67 of 92
ADUC7128
I2CxBYTE Register
Name I2C0BYT I2C1BYT Address 0xFFFF0824 0xFFFF0924 Default Value 0x00 0x00 Access RW RW
Preliminary Technical Data
I2CxALT is a hardware general call ID register used in slave mode
I2CxCFG Register
Name I2C0CFG I2C1CFG Address 0xFFFF082C 0xFFFF092C Default Value 0x00 0x00 Access RW RW
I2CxBYTE is a broadcast byte register.
I2CxALT Register
Name I2C0ALT I2C1ALT Address 0xFFFF0828 0xFFFF0928 Default Value 0x00 0x00 Access RW RW
I2CxCFG is a configuration register.
Table 65. I2C0CFG MMR Bit Descriptions
Bit 31 to 15 14 13 12 11 10 9 Description Reserved. These bits should be written by the user as 0. Enable stop interrupt. Set by the user to generate an interrupt upon receiving a stop condition and after receiving a valid start condition + matching address. Cleared by the user to disable the generation of an interrupt upon receiving a stop condition. Reserved. This bit should be written by the user as 0. Reserved. This bit should be written by the user as 0. Enable stretch SCL (holds SCL low). Set by the user to stretch the SCL line. Cleared by the user to disable stretching of the SCL line. Reserved. This bit should be written by the user as 0. Slave Tx FIFO request interrupt enable. Cleared by the user to generate an interrupt request just after the negative edge of the clock for the R/W bit. This allows the user to input data into the slave Tx FIFO if it is empty. At 400 ksps and the core clock running at 41.78 MHz, the user has 55 clock cycles to take appropriate action, taking interrupt latency into account. Set by the user to disable the slave Tx FIFO request interrupt. General call status bit clear. Set by the user to clear the general call status bits. Cleared automatically by hardware after the general call status bits have been cleared. Master serial clock enable bit. Set by user to enable generation of the serial clock in master mode. Cleared by user to disable serial clock in master mode. Loop back enable bit. Set by user to internally connect the transition to the reception to test user software. Cleared by user to operate in normal mode. Start back-off disable bit. Set by user in multi-master mode. If losing arbitration, the master immediately tries to retransmit. Cleared by user to enable start back-off. After losing arbitration, the master waits before trying to retransmit. Hardware general call enable. (Bit 3 must be set.) Set by user to enable hardware general call. Cleared by user to disable hardware general call. General call enable bit. Set by user to address every device on the IP2 bus. Cleared by user to operate in normal mode. Reserved. Master enable bit. Set by user to enable the master IP2 channel. Cleared by user to disable the master IP2 channel. Slave enable bit. Set by user to enable the slave IP2 channel. A slave transfer sequence is monitored for the device address in I2C0ID0, I2C0ID1, I2C0ID2, and I2C0ID3. If the device address is recognized, the part participates in the slave transfer sequence. Cleared by user to disable the slave IP2 channel.
PC PC PC PC PC
8 7 6 5 4 3 2 1 0
I2CxDIV Register
Name I2C0DIV I2C1DIV Address 0xFFFF0830 0xFFFF0930 Default Value 0x1F1F 0x1F1F Access RW RW
I2C1ID0 I2C1ID1 I2C1ID2 I2C1ID3
0xFFFF0938 0xFFFF093C 0xFFFF0940 0xFFFF0944
0x00 0x00 0x00 0x00
RW RW RW RW
I2CxDIV are the clock divider registers.
I2CxID0, I2CxID1, I2CxID2, and I2CxID3 are slave address device ID registers of I2Cx.
I2CxIDx Register
Name I2C0ID0 I2C0ID1 I2C0ID2 I2C0ID3 Address 0xFFFF0838 0xFFFF083C 0xFFFF0840 0xFFFF0844 Default Value 0x00 0x00 0x00 0x00 Access RW RW RW RW
I2CxCCNT Register
Name I2C0SSC I2C1SSC Address 0xFFFF0848 0xFFFF0948 Default Value 0x01 0x01 Access RW RW
I2CxCCNT is an 8-bit start/stop generation counter. It holds off SDA low for start and stop conditions.
Rev. PrA | Page 68 of 92
Preliminary Technical Data
I2CxFIF Register
Name I2C0FIF I2C1FIF Address 0xFFFF084C 0xFFFF094C Default Value 0x0000 0x0000 Access R R
ADUC7128
I2C0FIF is an FIFO status register.
Table 66. I2C0FIF MMR Bit Descriptions
Bit 15 to 10 9 8 7, 6 00 01 10 11 5, 4 00 01 10 11 3, 2 00 01 10 11 1, 0 00 01 10 11 Value Description Reserved. Master transmit FIFO flush. Set by the user to flush the master Tx FIFO. Cleared automatically once the master Tx FIFO is flushed. Slave transmit FIFO flush. Set by the user to flush the slave Tx FIFO. Cleared automatically once the slave Tx FIFO is flushed. Master Rx FIFO status bits. FIFO empty. Byte written to FIFO. 1 byte in FIFO. FIFO full. Master Tx FIFO status bits. FIFO empty. Byte written to FIFO. 1 byte in FIFO. FIFO full. Slave Rx FIFO status bits. FIFO empty. Byte written to FIFO. 1 byte in FIFO. FIFO full. Slave Tx FIFO status bits. FIFO empty. Byte written to FIFO. 1 byte in FIFO. FIFO full.
*
TP PT
Purchase of licensed IP2 components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips IP2 Patent Rights to use the ADUC7128 in an IP2 system, provided that the system conforms to the IP2 Standard Specification as defined by Philips.
PC PC PC PC
Rev. PrA | Page 69 of 92
ADUC7128
PROGRAMMABLE LOGIC ARRAY (PLA)
The ADUC7128 integrates a fully Programmable Logic Array (PLA) which consists of two independent but interconnected PLA blocks. Each block consists of eight PLA elements, which gives a total of 16 PLA elements. A PLA element contains a two-input lookup table that can be configured to generate any logic output function based on two inputs and a flip-flop as represented in Figure 48 below.
Preliminary Technical Data
of block 0 is fed back to the input 0 of mux 0 of element 0 of block 1. PLA Block 0 Element 0 1 2 3 4 5 6 7 Input P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P0.0 Output P1.7 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 8 9 10 11 12 13 14 15 PLA Block 1 Element Input P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Output P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7
0 2 3 1
A B
LOOK-UP TABLE
4
Table 67: element input/output
PLA MMRs interface
Figure 48: PLA element
The PLA peripheral interface consists on 21 MMRs: - PLAELMx: element0 to element 15 control registers, configure the input and output mux of each element, select the function in the lookup table and bypass/use the flip-flop. - PLACLK: clock selection for the flip-flops of block 0 and clock selection for the flip-flops of block 1 - PLAIRQ: enable IRQ0 or/and IRQ1 and select the source of the IRQ - PLAADC: PLA source fro ADC start conversion signal - PLADIN: data input MMR for PLA - PLAOUT: data output MMR for PLA. This register is always updated. A PLA tool is provided in the development system to easily configure the PLA.
In total, 30 GPIO pins are available on the ADUC7128 for the PLA. These include 16 input pins and 14 output pins. They need to be configured in the GPxCON register as PLA pins before using the PLA. Note that the comparator output is also included as one of the 16 input pins. The PLA is configured via a set of user MMRs and the output(s) of the PLA can be routed to the internal interrupt system, to the CONVBSTARTB signal of the ADC, to a MMR or to any of the 16 PLA output pins. The interconnection between the two blocks is supported by connecting output of element 7 of block 1 fed back to the input 0 of mux 0 of element 0 of block 0, and the output of element 7
Table 68: PLAELMx MMR Bit Descriptions Bit 31-11 10-9 Description Reserved Mux (0) control, select feedback from: 00 - element 15 01 - element 2 10 - element 4 11 - element 6 00 - element 1 01 - element 3 10 - element 5 11 - element 7 element 0 element 2 element 4 element 6 element 1 element 3 element 5 element 7 element 7 element 10 element 12 element 14 element 9 element 11 element 13 element 15 element 8 element 10 element 12 element 14 element 9 element 11 element 13 element 15 PLAELM0 PLAELM1 - 7 PLAELM8 PLAELM9-15
8-7
Mux (1) control, select feedback from:
6 5 4-1
Mux (3) control Set by user to select the output of mux (1) Cleared by user to select the bit value from PLADIN Mux (2) control Set by user to select the input pin of the particular element Cleared by user to select the output of mux (0) Look-up table control 0000 - 0 0001 - NOR 0010 - B AND NOT A
Rev. PrA | Page 70 of 92
Preliminary Technical Data
0011 - NOT A 0100 - A AND NOT B 0101 - NOT B 0110 - EXOR 0111 - NAND 1000 - AND 1001 - EXNOR 1010 - B 1011 - NOT A OR B 1100 - A 1101 - A OR NOT B 1110 - OR 1111 - 1 0 Mux (4) control Set by user to bypass the flip-flop Cleared by user to select the flip-flop. Cleared by default
ADUC7128
Table 69: PLACLK MMR Bit Descriptions Bit 7 6-4 Description Reserved Block1 clock source selection: 000 - GPIO clock on P0.5 001 - GPIO clock on P0.0 010 - GPIO clock on P0.7 011 - HCLK 100 - OCLK 101 - Timer 1 overflow 110 - Timer 4 overflow Other - Reserved Reserved Block0 clock source selection: 000 - GPIO clock on P0.5 001 - GPIO clock on P0.0 010 - GPIO clock on P0.7 011 - HCLK 100 - OCLK 101 - Timer 1 overflow 110 - Timer 4 overflow Other - Reserved
3 2-0
Table 70: PLAIRQ MMR Bit Descriptions Bit 15-13 12 11-8 Description Reserved PLA IRQ1 enable bit Set by user to enable IRQ1 output from PLA Cleared by user to disable IRQ1 output from PLA PLA IRQ1 source 0000 - PLA element 0 0001 - PLA element 1 ... 1111 - PLA element 15 Reserved PLA IRQ0 enable bit
Rev. PrA | Page 71 of 92
7-5 4
ADUC7128
3-0 Set by user to enable IRQ0 output from PLA Cleared by user to disable IRQ0 output from PLA PLA IRQ0 source 0000 - PLA element 0 0001 - PLA element 1 ... 1111 - PLA element 15
Preliminary Technical Data
Table 71: PLAADC MMR Bit Descriptions Bit 31-5 4 3-0 Description Reserved ADC start conversion enable bit Set by user to enable ADC start conversion from PLA Cleared by user to disable ADC start conversion from PLA ADC start conversion source 0000 - PLA element 0 0001 - PLA element 1 ... 1111 - PLA element 15
Table 72: PLADIN MMR Bit Descriptions Bit 31-16 15-0 Description Reserved Input Bit to element 15-0
Table 73: PLAOUT MMR Bit Descriptions Bit 31-16 15-0 Description Reserved Output Bit from element 15-0
Rev. PrA | Page 72 of 92
Preliminary Technical Data
PROCESSOR REFERENCE PERIPHERALS
INTERRUPT SYSTEM
There are 30 interrupt sources on the ADUC7128 which are controlled by the Interrupt Controller. Most interrupts are generated from the on-chip peripherals like ADC, UART, etc. and two additional interrupt sources are generated from external interrupt request pins, XIRQ0 and XIRQ1. The ARM7TDMI CPU core will only recognise interrupts as one of two types, a normal interrupt request IRQ and a fast interrupt request FIQ. All the interrupts can be masked separately. The control and configuration of the interrupt system is managed through nine interrupt-related registers, four dedicated to IRQ, four dedicated to FIQ. An additional MMR is used to select the programmed interrupt source. The bits in each IRQ and FIQ registers represent the same interrupt source as described in Table 74.
Table 74: IRQ/FIQ MMRs bit description
ADUC7128
26 27 28 29 30 External IRQ3 PWM Trip PLL Lock PLM RX PLM TX
IRQ
The IRQ is the exception signal to enter the IRQ mode of the processor. It is used to service general purpose interrupt handling of internal and external events. The four 32-bit registers dedicated to IRQ are: - IRQSIG, reflects the status of the different IRQ sources. If a peripheral generate an IRQ signal, the corresponding bit in the IRQSIG will be set, otherwise it is cleared. The IRQSIG bits are cleared when the interrupt in the particular peripheral is cleared. All IRQ sources can be masked in the IRQEN MMR. IRQSIG is read-only. - IRQEN, provides the value of the current enable mask. When bit is set to 1, the source request is enabled to create an IRQ exception. When bit is set to 0, the source request is disabled or masked which will not create an IRQ exception. To clear a bit in IRQEN, use the IRQCLR MMR. - IRQCLR, (write-only register) allows clearing the IRQEN register in order to mask an interrupt source. Each bit set to 1 will clear the corresponding bit in the IRQEN register without affecting the remaining bits. The pair of registers IRQEN and IRQCLR allows independent manipulation of the enable mask without requiring an atomic read-modifywrite. - IRQSTA, (read-only register) provides the current enabled IRQ source status. When set to 1 that source should generate an active IRQ request to the ARM7TDMI core. There is no priority encoder or interrupt vector generation. This function is implemented in software in a common interrupt handler routine. All 32 bits are logically OR'ed to create the IRQ signal to the ARM7TDMI core.
Bit 0 1
Description FIQ source SWI: not used in IRQEN/CLR and FIQEN/CLR Timer 0 Timer 1 Wake Up timer - Timer 2 Watchdog timer - Timer 3 Timer 4 Flash Controler 0 Flash Controler 1 ADC Quadrature Encoder IP2 Slave IP2 Slave IP2 Master IP2 Master SPI Slave SPI Master UART 0 UART 1 External IRQ0 Comparator PSM External IRQ1 PLA IRQ0 PLA IRQ1 External IRQ2
PC0 PC1 PC0 PC1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
FIQ
The FIQ (Fast Interrupt reQuest) is the exception signal to enter the FIQ mode of the processor. It is provided to service data transferor communication channel tasks with low latency. The FIQ interface is identical to the IRQ interface providing the second level interrupt (highest priority). Four 32-bit registers are dedicated to FIQ, FIQSIG, FIQEN, FIQCLR and FIQSTA. Bit 31 to 1 of FIQSTA are logically OR'ed to create the FIQ signal to the core and the bit 0 of both the FIQ and IRQ registers (FIQ source). The logic for FIQEN and FIQCLR will not allow an interrupt source to be enabled in both IRQ and FIQ masks. A bit set to `1' in FIQEN will, as a side-effect, clear the same bit in IRQEN. A bit set to `1' in IRQEN will, as a side-effect, clear the same bit in
Rev. PrA | Page 73 of 92
ADUC7128
FIQEN. An interrupt source can be disabled in both IRQEN and FIQEN masks.
Preliminary Technical Data
The 32-bit register dedicated to software interrupt is SWICFG described in Table 75. This MMR allows the control of programmed source interrupt.
Programmed interrupts
As the programmed interrupts are non-mask-able, they are controlled by another register, SWICFG, which write into both IRQSTA and IRQSIG registers or/and FIQSTA and FIQSIG registers at the same time. Table 75: SWICFG MMR Bit Descriptions Bit 31-3 2 1 0 Description Reserved Programmed Interrupt-FIQ Setting/clearing this bit correspond in setting/clearing bit 1 of FIQSTA and FIQSIG Programmed Interrupt-IRQ Setting/clearing this bit correspond in setting/clearing bit 1 of IRQSTA and IRQSIG Reserved
Note that any interrupt signal must be active for at least the equivalent of the interrupt latency time, to be detected by the interrupt controller and to be detected by user in the IRQSTA/FIQSTA register.
Rev. PrA | Page 74 of 92
Preliminary Technical Data
TIMERS
The ADUC7128 has five general purpose Timer/Counters: - Timer0, - Timer1, - Timer2 or Wake-up Timer, - Timer3 or Watchdog Timer. - Timer4 The five timers in their normal mode of operation can be either free-running or periodic. - In free-running mode the counter decrements/increments from the maximum/minimum value until zero/full scale and starts again at the maximum /minimum value. - In periodic mode the counter decrements/increments from the value in the Load Register(TxLD MMR,) until zero/full scale and starts again at the value stored in the Load Register. The value of a counter can be read at any time by accessing its value register (TxVAL). Timers are started by writing in the Control register of the corresponding timer (TxCON). In normal mode, an IRQ is generated each time the value of the counter reaches zero, if counting down, or full-scale, if counting up. An IRQ can be cleared by writing any value to Clear register of the particular timer (TxICLR). Table 76. : Event Selection Numbers ES 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 Interrupt Number 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
ADUC7128
Name RTOS Timer (Timer 0) GP Timer 0 (Timer 1) Wake Up Timer (Timer 2) Watchdog Timer (Timer 3) GP Timer 1 (Timer 4) Flash Control 0 Flash Control 1 ADC Channel Quadrature Encoder I2C Slave0 I2C Slave1 I2C Master0 I2C Master1 SPI Slave SPI Master UART0 UART1 External irq0
Rev. PrA | Page 75 of 92
ADUC7128
TIMER0 - LIFE-TIME TIMER
Timer0 is a general purpose 48-bit count-up, or a 16-bit count up/down timer with a programmable prescalar. Timer0 is clocked from the core clock, with a prescalar of 1,16, 256 or 32768. This gives a minimum resolution of 22ns when the core is operating at 41.78MHz, and with a prescalar of 1. In 48-bit mode, Timer0 counts up from zero. The current counter value may be read from T0VAL0 and T0VAL1. In 16-Bit mode,Timer0 may count up or count down. A 16-bit value may be written to T0LD which will be loaded into the counter. The current counter value may be read from T0VAL0. Timer0 has a capture register (T0CAP), which may be triggered by a selected IRQ's source initial assertion. Once triggered, the current timer value is copied to T0CAP, and the timer keeps running. This feature can be used to determine the assertion of an event with more accuracy than by servicing an interrupt alone.
Preliminary Technical Data
Timer0 reloads the value from T0LD either when TIMER0 overflows, or immediately when T0ICLR is written. Timer0 interface consists of six MMRS: - T0LD is a 16-bit register which holds the 16 bit value that is loaded into the counter. Only available in 16-bit mode. - T0CAP is a 16-bit register which holds the 16-bit value captured by an enabled IRQ event. Only available in 16-bit mode. - T0VAL0/T0VAL1 are 16-bit and 32-bit registers which hold the 16 least significant bits and 32 most significant bits respectively. T0VAL0 and T0VAL1 is read-only. In 16-bit mode 16-bit T0VAL0 is used. In 48-bit mode both 16-bit T0VAL0 and 32-bit T0VAL1 are used. - T0ICLR is an 8-bit register. Writing any value to this register will clear the interrupt. Only available in 16-bit mode. - T0CON is the configuration MMR described in Table 77.
16-bit Load
Core Clock Frequency
Prescaler 1 , 16, 256 or 32768
48-bit Up Counter 16-Bit Up/Down Counter
Timer0IRQ
Timer0 Value IRQ[31:0] Capture
Figure 49 : Timer 0 block diagram
Timer0 Value Register :
Name : T0VAL0/T0VAL1 Address : 0xFFFF0304, 0xFFFF0308 Default Value : 0x00, 0x00 Access : Read Only Function : T0VAL0 and T0VAL1 are 16-bit and 32-bit registers which hold the 16 least significant bits and 32 most significant bits respectively. T0VAL0 and T0VAL1 is read-only. In 16-bit mode 16-bit T0VAL0 is used. In 48-bit mode both 16bit T0VAL0 and 32-bit T0VAL1 are used.
Timer0 Capture Register :
Name : Address : T0CAP 0xFFFF0314
Default Value : 0x00 Access : Read Only Function : This is a 16-bit register which holds the 16bit value captured by an enabled IRQ event. Only available in 16-bit mode.
Rev. PrA | Page 76 of 92
Preliminary Technical Data
Timer0 Control Register :
Name : Address : Default Value : Access : Function : T0CON 0xFFFF030C 0x00 Read/Write The 17-bit MMR configures the mode of operation of Timer0
ADUC7128
Table 77 : T0CON MMR Bit Descriptions
Bit 31-18 17
Description Reserved Event Select bit: Set by user to enable time capture of an event Cleared by user to disable time capture of an event Event select range, 0 to 31 The events are as described in the introduction to the timers.. Reserved Reserved Count up: ( Only available in 16Bit Mode ) Set by user for timer 0 to count up Cleared by user for timer 0 to count down. ( Default ) Timer0 enable bit: Set by user to enable timer 0 Cleared by user to disable timer 0. ( Default ) Timer 0 mode: Set by user to operate in periodic mode Cleared by user to operate in free-running mode. ( Default ) Reserved Timer0 Mode of Operation: 0 16 Bit operation ( Default ) 1 48 Bit Operation Prescalar: 0000 Source clock / 1 ( Default ) 0100 Source clock / 16 1000 Source clock / 256 1111 Source clock / 32768
16-12 11 10-9 8
7
6
5 4
3-0
Timer0 Load Registers:
Name : Address : Default Value : Access : T0LD 0xFFFF0300 0x00 Read/Write
Timer0 Clear Register :
Name : Address : T0ICLR 0xFFFF0310
Function : T0LD0 is a 16-bit register which holds the 16 bit value that is loaded into the counter. Only available in 16-bit mode.
Default Value : 0x00 Access : Write Only Function : This 8-bit, write-only MMR is written (with any value) by user code to refresh(reload) Timer0.
Rev. PrA | Page 77 of 92
ADUC7128
TIMER1
Timer1 is a 32-bit general purpose timer, count-down or countup, with a programmable pre-scalar. The pre-scalar source can the 32kHz oscillator, the core clock, or from one of two external GPIO. This source can be scaled by a factor of 1, 16, 256 or 32768. This gives a minimum resolution of 42ns when operating at CD zero, the core is operating at 41.78MHz, and with a pre-scalar of 1 ( Ignoring external GPIO). The counter can be formatted as a standard 32-bit value or as Hours:Minutes:Seconds:Hundreths. Timer1 has a capture register (T1CAP), which can be triggered by a selected IRQ's source initial assertion. Once triggered, the current timer value is copied to T1CAP, and the timer keeps running. This feature can be used to determine the assertion of an event with increased accuracy. Timer1 interface consists of five MMRS: - T1LD, T1VAL and T1CAP are 32-bit registers and hold 32bit unsigned integers. T1VAL and T1CAP are read-only. - T1ICLR is an 8-bit register. Writing any value to this register will clear the timer1 interrupt. - T1CON is the configuration MMR described in below. NOTE: If the part is in a low power mode, and Timer1 is clocked from the GPIO or low power oscillator source then, Timer1 will continue to be operate.
Preliminary Technical Data
Timer1 reloads the value from T1LD either when TIMER01 overflows, or immediately when T1ICLR is written.
Timer1 Load Registers:
Name : T1LD Address : 0xFFFF0320 Default Value : 0x00000 Access : Read/Write Function : T1LD is a 32 bit register which holds the 32 bit value that is loaded into the counter.
Timer1 Clear Register :
Name : T1ICLR Address : 0xFFFF032C Default Value : 0x00 Access : Write Only Function : This 8-bit, write-only MMR is written (with any value) by user code to refresh(reload) Timer1.
Timer1 Value Register :
Name : T1VAL Address : 0xFFFF0324 Default Value : 0x0000 Access : Read Only Function : T1VAL is a 32-bit register which holds the current value of Timer1
32-bit Load
32.768kHz Oscillator Core Clock Frequency GPIO GPIO
Prescaler 1 , 16, 256 or 32768
32-bit Up/Down Counter
Timer1IRQ
Timer1 Value
IRQ[31:0]
Capture
Figure 50 : Timer 1 Block Diagram
Rev. PrA | Page 78 of 92
Preliminary Technical Data
Timer1 Capture Register :
Name : T1CAP Address : 0xFFFF0330 Default Value : 0x00 Access : Read Only Function : This is a 32-bit register which holds the 32bit value captured by an enabled IRQ event.
ADUC7128
Timer1 Control Register :
Name : T1CON Address : 0xFFFF0328 Default Value : 0x0000 Access : Read/Write Function : This 32-bit MMR configures the mode of operation of Timer1
Table 78 : T1CON MMR Bit Descriptions
Bit 31-18 17
Description Reserved Should be set to `0' by the user Event Select bit: Set by user to enable time capture of an event Cleared by user to disable time capture of an event Event select range, 0 to 31 The events are as described in the introduction to the timers. Clock select: 000 Core clock ( Default ) 001 32.768kHz Oscillator 010 P1.0 011 P0.6 Count up: Set by user for timer 1 to count up Cleared by user for timer 1 to count down. ( Default ) Timer1 enable bit: Set by user to enable timer 1 Cleared by user to disable timer 1. ( Default ) Timer 1 mode: Set by user to operate in periodic mode Cleared by user to operate in free-running mode. ( Default ) Format: 00 Binary ( Default ) 01 Reserved 10 Hr:Min:Sec:Hundredths - 23 hours to 0 hour 11 Hr:Min:Sec:Hundredths - 255 hours to 0 hour Pre-Scalar: 0000 Source clock / 1 ( Default ) 0100 Source clock / 16 1000 Source clock / 256 1111 Source clock / 32768
16-12 11-9
8
7
6
5-4
3-0
Rev. PrA | Page 79 of 92
ADUC7128
TIMER2 - WAKE-UP TIMER
Timer2 is a 32-bit wake-up timer, count-down or count-up, with a programmable prescalar. The pre-scalar is clocked directly from 1 of 4 clock sources, namely, the Core Clock (default selection), the internal 32.768kHz Oscillator, External 32.768kHz Watch Crystal, or the core clock. The selected clock source can be scaled by a factor of 1, 16, 256 or 32768. The wake-up timer will continue to run when the core clock is disabled. This gives a minimum resolution of 22ns when operating at CD zero, the core is operating at 41.78MHz, and with a prescalar of 1. Capture of the current timer value is enabled if the Timer2 interrupt is enabled via IRQEN[4]. The counter can be formatted as plain 32-bit value or as Hours:Minutes:Seconds:Hundreths. Timer2 reloads the value from T2LD either when TIMER2 overflows, or immediately when T2ICLR is written. Timer2 interface consists of four MMRS: - T2LD and T2VAL are 32-bit registers and hold 32-bit unsigned integers. T2VAL is read-only. - T2ICLR is an 8-bit register. Writing any value to this register will clear the timer2 interrupt. - T2CON is the configuration MMR described in Table 79. Name : Address : Default Value : Access :
Preliminary Technical Data
Timer2 Load Registers:
T2LD 0xFFFF0340 0x00000 Read/Write
Function : T2LD is a 32 bit register which holds the 32 bit value that is loaded into the counter.
Timer2 Clear Register :
Name : T2ICLR Address : 0xFFFF034C Default Value : 0x00 Access : Write Only Function : This 8-bit, write-only MMR is written (with any value) by user code to refresh(reload) Timer2.
Timer2 Value Register :
Name : T2VAL Address : 0xFFFF0344 Default Value : 0x0000 Access : Read Only Function : T2VAL is a 32-bit register which holds the current value of Timer2
External 32kHz Oscillator Internal 32kHz Oscillator Core Clock Prescaler 1, 16, 256 or 32768
32-bit Load
Timer2IRQ 32-bit Up/Down Counter
Timer2 Value
Figure 51 : Timer 2 block diagram
Rev. PrA | Page 80 of 92
Preliminary Technical Data
Timer2 Control Register :
Name : Address : Default Value : Access : Function : T2CON 0xFFFF0348 0x0000 Read/Write This 32-bit MMR configures the mode of operation of Timer2
Table 79 : T2CON MMR Bit Descriptions
ADUC7128
Bit 31-11 10-9
Description Reserved Clock Source Select: 00 Core Clock ( Default ) 01 Inernal 32.768kHz Oscillator 10 External 32.768kHz Watch Crystal 11 External 32.768kHz Watch Crystal Count up: Set by user for timer 2 to count up Cleared by user for timer 2 to count down. ( Default ) Timer2 enable bit: Set by user to enable timer 2 Cleared by user to disable timer 2. ( Default ) Timer 2 mode: Set by user to operate in periodic mode Cleared by user to operate in free-running mode. ( Default ) Format: 00 Binary ( Default ) Reserved 01 10 Hr:Min:Sec:Hundredths - 23 hours to 0 hour 11 Hr:Min:Sec:Hundredths - 255 hours to 0 hour Prescalar: 0000 Source clock / 1 ( Default ) 0100 Source clock / 16 1000 Source clock / 256 ( This setting should be used in conjunction Timer2 Formats 1,0 and 1,1 ) 1111 Source clock / 32768
8
7
6
5-4
3-0
Rev. PrA | Page 81 of 92
ADUC7128
TIMER3 - WATCHDOG TIMER
Timer3 has two modes of operation, normal mode and watchdog mode. The Watchdog timer is used to recover from an illegal software state. Once enabled it requires periodic servicing to prevent it from forcing a reset of the processor. Timer3 reloads the value from T3LD either when TIMER3 overflows, or immediately when T3ICLR is written.
Preliminary Technical Data
memory page erase cycles, which require 20ms to complete a single page erase cycle, and Kernel Execution.. If T3VAL reaches 0, a reset or an interrupt occurs, depending on T3CON[1]. To avoid a reset or an interrupt event, any value must be written to T3ICLR before T3VAL reaches zero. This reloads the counter with T3LD and begins a new timeout period. Once watchdog mode is entered, T3LD and T3CON are writeprotected. These two registers can not be modified until a Power On Reset event, resets the Watchdog Timer, after any other reset event, the Watchdog Timer continues to count. The Watchdog Timer should be configured in the initial lines of user code to avoid an infinite loop of Watchdog Resets. User software should only configure a minimum timeout period of 30msecs. Timer3 is automatically halted during JTAG debug access and will only recommence counting once JTAG has relinquished control of the ARM7 core. By default, Timer3 continues to count during power-down. This may be disabled by setting bit zero in T3CON. It is recommended that the default value is used, i.e. that the Watchdog Timer continues to count during power-down.
Normal mode:
The Timer3 in normal mode is identical to Timer0, in 16-bit mode of operation, except for the clock source. The clock source is the 32.768kHz oscillator and can be scaled by a factor of 1, 16, or 256. Timer3 also features a capture facility, which allows the capture of the current timer value if the Timer2 interrupt is enabled via IRQEN[5].
Watchdog mode:
Watchdog mode is entered by setting T3CON[5]. Timer3 decrements from the timeout value present in T3LD Register until zero. The maximum timeout is 512 seconds, using the maximum pre-scalar /256 and full-scale in T3LD. User software should only configure a minimum timeout period of 30msecs. This is to avoid any conflict with Flash/EE
16-bit Load
Low Power 32.768kHz
Prescaler 1, 16, 256
16-bit Up/Down Counter
Watchdog Reset Timer3IRQ
Timer3 Value
Figure 52 : Timer3 Block Diagram
Timer3 Interface:
Timer3 interface consists of four MMRS: - T3CON is the configuration MMR described in Table 80 - T3LD and T3VAL are 16-bit registers (bit 0 to 15) and hold 16-bit unsigned integers. T3VAL is read-only. - T3ICLR is an 8-bit register. Writing any value to this register will clear the Timer3 interrupt in normal mode or will reset a new timeout period in watchdog mode
Timer3 Load Register :
Name : Address : Default Value : Access : Function : value. T3LD 0xFFFF0360 0x03D7 Read/Write This 16-bit MMR holds the Timer3 reload
Rev. PrA | Page 82 of 92
Preliminary Technical Data
Timer3 Value Register :
Name : T3VAL Address : 0xFFFF0364 Default Value : 0x03D7 Access : Read Only Function : This 16-bit, read-only MMR holds the currentTimer3 count value.
ADUC7128
Timer3 Clear Register :
Name : T3ICLR Address : 0xFFFF036C Default Value : 0x00 Access : Write Only Function : This 8-bit, write-only MMR is written (with any value) by user code to refresh(reload) Timer3 in watchdog mode to prevent a watchdog timer reset event.
Timer3 Control Register :
Name : Address : Default Value : Access : Function : T3CON 0xFFFF0368 0x00 Read/Write Once Only The 16-bit MMR configures the mode of operation of Timer3 as is described in detail in Table 80
Table 80 : T3CON MMR Bit Definition
Bit 16-9 8
Description These bits are reserved and should be written as 0 by user code Count Up/Down Enable Set by user code to configure Timer3 to count up Cleared by user code to configure Timer3 to count down.
7
Timer3 Enable Set by user code to enable Timer 3 Cleared by user code to disable Timer 3. .
6
Timer3 Operating Mode Set by user code to configure Timer3 to operate in periodic mode Cleared by user to configure Timer3 to operate in free-running mode.
5
Watchdog Timer Mode Enable Set by user code to enable watchdog mode Cleared by user code to disable watchdog mode Secure clear bit. Set by user to use the secure clear option. Cleared by user to disable the secure clear option by default. Timer3 Clock(32.768kHz) Pre-Scalar 00 Source clock / 1 ( Default ) 01 Reserved 10 Reserved 11 Reserved Watchdog Timer IRQ Enable Set by user code to produce an IRQ instead of a reset when the watchdog reaches 0 Cleared by user code to disable the IRQ option.
4
3-2
1
0
PD_OFF Set by the user code to stop Timer3 when the peripherals are powered down via bit 4 in the POWCON MMR. Cleared by the user code to enable Timer3 when the peripherals are powered down via bit 4 in the POWCON MMR.
Rev. PrA | Page 83 of 92
ADUC7128
Secure Bit Clear (Watchdog Mode Only)
Preliminary Technical Data
The secure clear bit is provided for a higher level of protection. When set, a specific sequential value must be written to T3ICLR to avoid a watchdog reset. The value is a sequence generated by the 8-bit linear feedback shift register (LFSR) polynomial = X8 + X6 + X5 + X + 1 as shown Figure 53.
Q 7 CLOCK
D
Q 6
D
Q 5
D
Q 4
D
Q 3
D
Q 2
D
Q 1
D
Q 0
D
04955-038
Figure 53. 8-Bit LFSR
The initial value or seed is written to T3ICLR before entering watchdog mode. After entering watchdog mode, a write to T3ICLR must match this expected value. If it matches, the LFSR is advanced to the next state when the counter reload happens. If it fails to match the expected state, reset is immediately generated, even if the count has not yet expired. The value 0x00 should not be used as an initial seed due to the properties of the polynomial. The value 0x00 is always guaranteed to force an immediate reset. The value of the LFSR can not be read; it must be tracked/generated in software. Example of a sequence: 1. 2. 3. 4. 5. Enter initial seed, 0xAA, in T3ICLR before starting timer3 in watchdog mode. Enter 0xAA in T3ICLR; timer3 is reloaded. Enter 0x37 in T3ICLR; timer3 is reloaded. Enter 0x6E in T3ICLR; timer3 is reloaded. Enter 0x66. 0xDC was expected; the watchdog reset the chip.
Rev. PrA | Page 84 of 92
Preliminary Technical Data
TIMER4
Timer4 is a 32-bit general purpose timer, count-down or countup, with a programmable pre-scalar. The pre-scalar source can the 32kHz oscillator, the core clock, or from one of two external GPIO. This source can be scaled by a factor of 1, 16, 256 or 32768. This gives a minimum resolution of 42ns when operating at CD zero, the core is operating at 41.78MHz, and with a pre-scalar of 1 ( Ignoring external GPIO). The counter can be formatted as a standard 32-bit value or as Hours:Minutes:Seconds:Hundreths. Timer4 has a capture register (T4CAP), which can be triggered by a selected IRQ's source initial assertion. Once triggered, the current timer value is copied to T4CAP, and the timer keeps running. This feature can be used to determine the assertion of an event with increased accuracy. Timer4 interface consists of five MMRS: - T4LD, T4VAL and T4CAP are 32-bit registers and hold 32bit unsigned integers. T4VAL and T4CAP are read-only. - T4ICLR is an 8-bit register. Writing any value to this register will clear the timer1 interrupt. - T4CON is the configuration MMR described in Table 81. NOTE: If the part is in a low power mode, and Timer4 is clocked from the GPIO or oscillator source then, Timer4 will continue to be operate.
ADUC7128
overflows, or immediately when T4ICLR is written.
Timer4 Load Registers:
Name : Address : Default Value : Access : T4LD 0xFFFF0380 0x00000 Read/Write
Function : T4LD is a 32 bit register which holds the 32 bit value that is loaded into the counter.
Timer4 Clear Register :
Name : T4ICLR Address : 0xFFFF038C Default Value : 0x00 Access : Write Only Function : This 8-bit, write-only MMR is written (with any value) by user code to refresh(reload) Timer4.
Timer4Value Register :
Name : T4VAL Address : 0xFFFF0384 Default Value : 0x0000 Access : Read Only Function : T4VAL is a 32-bit register which holds the current value of Timer4
Timer4 reloads the value from T4LD either when TIMER04
32-bit Load 32.768kHz Oscillator Core Clock Frequency GPIO GPIO Timer1 Value Prescaler 1 , 16, 256 or 32768
32-bit Up/Down Counter
Timer4IRQ
IRQ[31:0]
Capture
Figure 54 : Timer 4 Block Diagram
Rev. PrA | Page 85 of 92
ADUC7128
Timer4 Capture Register :
Name : T4CAP Address : 0xFFFF0390 Default Value : 0x00 Access : Read Only Function : This is a 32-bit register which holds the 32bit value captured by an enabled IRQ event.
Preliminary Technical Data
Timer4 Control Register :
Name : T4CON Address : 0xFFFF0388 Default Value : 0x0000 Access : Read/Write Function : This 32-bit MMR configures the mode of operation of Timer4
Table 81 : T4CON MMR Bit Descriptions
Bit 31-18 17
Description Reserved Should be set to `0' by the user Event Select bit: Set by user to enable time capture of an event Cleared by user to disable time capture of an event Event select range, 0 to 31 The events are as described in the introduction to the timers. Clock select: 000 Core clock ( Default ) 001 32.768kHz Oscillator 010 P4.6 011 P4.7 Count up: Set by user for timer 4 to count up Cleared by user for timer 4 to count down. ( Default ) Timer 4 enable bit: Set by user to enable timer 4 Cleared by user to disable timer 4. ( Default ) Timer 4 mode: Set by user to operate in periodic mode Cleared by user to operate in free-running mode. ( Default ) Format: 00 Binary ( Default ) 01 Reserved 10 Hr:Min:Sec:Hundredths - 23 hours to 0 hour 11 Hr:Min:Sec:Hundredths - 255 hours to 0 hour Pre-Scalar: 0000 Source clock / 1 ( Default ) 0100 Source clock / 16 1000 Source clock / 256 1111 Source clock / 32768
16-12 11-9
8
7
6
5-4
3-0
Rev. PrA | Page 86 of 92
Preliminary Technical Data
ADUC7128 Hardware Design considerations
ADUC7128
Finally, on the CSP package, the paddle on the bottom of the package should be soldered to a metal plate to provide mechanical stability. This metal plate should be connected to ground.
POWER SUPPLIES
The ADUC7128 operational power supply voltage range is 3.0V to 3.6V. Separate analog and digital power supply pins (AVDD and IOVDD, respectively) allow AVDD to be kept relatively free of noisy digital signals often present on the system IOVDD line. In this mode, the part can also operate with split supplies; that is, using different voltage supply levels for each supply. For example, this means that the system can be designed to operate with a IOVDD voltage level of 3.3 V while the AVDD level can be at 3 V, or vice versa if required. A typical split supply configuration is shown in Figure 55.
DIGITAL SUPPLY + 10F ANALOG SUPPLY 10F + IOV DD LV DD 0.1F 0.47F IOGND PV DD DACVDD GND REF DACGND AGND REFGND 0.1F AV DD
Linear Voltage regulator
The ADUC7128 requires a single 3.3V supply but the core logic requires a 2.5V supply. An on-chip linear regulator generates the 2.5V from IOVBDDB for the core logic. LVBDDB pin 21 is the 2.5V supply for the core logic. The DAC logic and PLL logic also require a 2.5V supply, this must be connected externally from the LVdd pin to the DACVdd and PVdd pins. An external compensation capacitor of 0.47 F must be connected between LVBDDB and DGND (as close as possible to these pins) to act as a tank of charge as shown inFigure 57. 0.1 F decoupling capacitors also must be placed as close as possible to the PVdd and DACVdd pins.
0.1F
LV DD 0.1F 0.47F PVDD DACVDD
Figure 55: External dual supply connections
As an alternative to providing two separate power supplies, the user can help keep AVDD quiet by placing a small series resistor and/or ferrite bead between it and IOVDD, and then decoupling AVDD separately to ground. An example of this configuration is shown in Figure 56. With this configuration other analog circuitry (such as op amps, voltage reference, and so on) can be powered from the AVDD supply line as well.
DIGITAL SUPPLY + 10uF
Figure 57: voltage regulator connections
The LVBDDB pin should not be used for any other chip. It is also recommended that the IOVBDDB has excellent power supply decoupling this to help improving line regulation performance of the on-chip voltage regulator.
ADuC7229
BEAD 1.6V 10uF
GROUNDING AND BOARD LAYOUT RECOMMENDATIONS
As with all high resolution data converters, special attention must be paid to grounding and PC board layout of ADUC7128based designs in order to achieve optimum performance from the ADCs and DAC. Although the ADUC7128 has separate pins for analog and digital ground (AGND and IOGND), the user must not tie these to two separate ground planes unless the two ground planes are connected together very close to the ADUC7128, as illustrated in the simplified example of Figure 58a. In systems where digital and analog ground planes are connected together somewhere else (at the system's power supply for example), they cannot be connected again near the ADUC7128 since a ground loop would result. In these cases, tie the ADUC7128's AGND and IOGND Pins all to the analog ground plane, as illustrated in Figure 58b. In systems with only one ground plane, ensure that the digital and analog components are physically separated onto separate halves of the board such that digital return currents do not flow near analog circuitry and vice versa. The ADUC7128 can then be placed between the
IOVDD LVDD 0.1F 0.47F IOGND PVDD DACVDD
AVDD
0.1F
GNDREF DACGND AGND REFGND
0.1F
Figure 56: external single supply connections
Notice that in both Figure 56 and Figure 57, a large value (10 F) reservoir capacitor sits on IOVDD and a separate 10 F capacitor sits on AVDD. Also, local small-value (0.1 F) capacitors are located at each AVBDDB and IOVDD pin of the chip. As per standard design practice, be sure to include all of these capacitors, and ensure the smaller capacitors are close to each AVDD pin with trace lengths as short as possible. Connect the ground terminal of each of these capacitors directly to the underlying ground plane. It should also be noted that, at all times, the analog and digital ground pins on the ADUC7128 must be referenced to the same system ground reference point.
Rev. PrA | Page 87 of 92
ADUC7128
digital and analog sections, as illustrated in Figure 58c.
Preliminary Technical Data
XCLKI and XCLKO as shown Figure 59. External capacitors should be connected as per the crystal manufacturer's recommendations. Note that the crystal pads already have an internal capacitance of typically 10pF. User should ensure that the total capacitance (10pF internal + external capacitance) doesn't exceed the manufacturer rating. This 32kHz crystal allows the PLL to lock correctly to give a frequency of 41.78 MHz. If no external crystal is present, the internal oscillator will be used to give a frequency of 41.78MHz 3% typically.
XCLKO 12pF
a.
PLACE ANALOG COMPONENTS HERE
PLACE DIGITAL COMPONENTS HERE
AGND
DGND
b.
PLACE ANALOG COMPONENTS HERE AGND
PLACE DIGITAL COMPONENTS HERE DGND
32.768kHz 12pF
XCLKI
TO INTERNAL PLL
Figure 59: external parallel resonant crystal connections
c.
PLACE ANALOG COMPONENTS HERE GND
PLACE DIGITAL COMPONENTS HERE
To use an external source clock input instead of the PLL, bit 1 and bit 0 of PLLCON must be modified. The external clock uses pin 17, XCLK.
XCLKI
Figure 58:. System grounding schemes
In all of these scenarios, and in more complicated real-life applications, keep in mind the flow of current from the supplies and back to ground. Make sure the return paths for all currents are as close as possible to the paths the currents took to reach their destinations. For example, do not power components on the analog side of Figure 58b with IOVDD since that would force return currents from IOVDD to flow through AGND. Also, try to avoid digital currents flowing under analog circuitry, which could happen if the user placed a noisy digital chip on the left half of the board in Figure 58c. Whenever possible, avoid large discontinuities in the ground plane(s) (such as are formed by a long trace on the same layer), since they force return signals to travel a longer path. And of course, make all connections to the ground plane directly, with little or no trace separating the pin from its via to ground. If the user plans to connect fast logic signals (rise/fall time < 5 ns) to any of the ADUC7128's digital inputs, add a series resistor to each relevant line to keep rise and fall times longer than 5 ns at the ADUC7128 input pins. A value of 100 or 200 is usually sufficient to prevent high speed signals from coupling capacitively into the ADUC7128 and affecting the accuracy of ADC conversions.
EXTERNAL CLOCK SOURCE
XCLK
TO FREQUENCY DIVIDER
Figure 60:connecting an external clock source
Whether using the internal PLL or an external clock source, the ADUC7128's specified operational clock speed range is 50kHz to 41.78 MHz to ensure correct operation of the analog peripherals and Flash/EE.
POWER-ON RESET OPERATION
An internal POR (Power-On Reset) is implemented on the ADUC7128. For LVDD below 2.45 V, the internal POR will hold the ADUC7128 in reset. As LVDD rises above 2.45 V, an internal timer will time out for typically 64 ms before the part is released from reset. The user must ensure that the power supply IOVDD has reached a stable 3.0 V minimum level by this time. Likewise on power-down, the internal POR will hold the ADUC7128 in reset until LVDD has dropped below 2.45V. Figure 61 illustrates the operation of the internal POR in detail.
CLOCK OSCILLATOR
The clock source for the ADUC7128 can be generated by the internal PLL or by an external clock input. To use the internal PLL, connect a 32.768kHz parallel resonant crystal between
Rev. PrA | Page 88 of 92
Preliminary Technical Data
3.3V IOVDD 2.4V TYP
ADUC7128
2.6V 2.4V TYP
LVDD 64ms TYP
POR 0.12ms TYP MRST
Figure 61:. ADUC7128 Internal Power-on-Reset operation
TYPICAL SYSEM CONFIGURATION
A typical ADUC7128 configuration is shown in Figure 62. It summarizes some of the hardware considerations discussed in the previous paragraphs.
Figure 62:. Typical System Configuration
Rev. PrA | Page 89 of 92
ADUC7128
DEVELOPMENT TOOLS
An entry level, low cost development system is available for the ADUC7128 family. This system consists of the following PCbased (Windows(R) compatible) hardware and software development tools: Hardware: - ADUC7128 Evaluation board - Serial Port programming cable - JTAG emulator Software: - Integrated Development Environment, incorporating assembler, compiler and non intrusive JTAG-based debugger - Serial Downloader software - Example Code Miscellaneous: - CD-ROM Documentation
Preliminary Technical Data
IN-CIRCUIT SERIAL DOWNLOADER
The Serial Downloader is a Windows application that allows the user to serially download an assembled program to the onchip program FLASH/EE memory via the serial port on a standard PC.
Rev. PrA | Page 90 of 92
Preliminary Technical Data
OUTLINE DIMENSIONS
ADUC7128
On the CSP package, the paddle on the bottom of the package should be soldered to a metal plate to provide mechanical stability. This metal plate should be connected to ground.
6 4 -Lead Lead Frame Chip Scale Package [ LFCSP] 9 x 9 mm Body ( CP-6 4 -1 ) Dimensions shown in millimet ers 9 .00 BSC SQ 0 .3 0 0 .2 5 0 .1 8
64 1
0 .6 0 MAX 0 .6 0 MAX
49 48
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP V IEW
8 .7 5 BSC SQ
EXPOSED PAD ( BOT TOM VIEW)
4 .8 5 4 .7 0 SQ 4 .5 5
0 .4 5 0 .4 0 0 .3 5
33 32
16 17
1 .0 0 0 .8 5 0 .8 0
1 2 MAX
0 .8 0 MAX 0 .6 5 TYP 0 .05 MAX 0 .02 NOM 0 .5 0 BSC
7 .5 0 REF
SEATING PLANE
0 .2 0 REF
COMPLIANT TO JEDEC STANDARDS MO-2 2 0 -VMMD
Figure 63.
64-Lead Frame Chip Scale Package [LFCSP] (CP-64-1)--Dimensions shown in millimetres
Rev. PrA | Page 91 of 92
ADUC7128
NOTES
Preliminary Technical Data
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06020-0-3/06(PrA)
Rev. PrA | Page 92 of 92

▲Up To Search▲

Price & Availability of ADUC7128

	To Download ADUC7128 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .